Training Insights - RTL-to-GDSII: Creativity Meets Engineering in Chip Design

The world of chip design is a captivating blend of creativity and engineering skills, so the heart of this complicated process lies in the RTL-to-GDSII flow, where the visionary ideas of engineers or designers are translated into physical chips that can boost our modern digital landscape. In this blog post, we will explore how the RTL-to-GDSII flow brings together the realms of creativity and engineering.

Let's first investigate all the stages (along with the Cadence tools used in each stage) in the RTL-to-GDSII flow:

1. Design and Verification stage: An RTL code is designed with hardware description language, which is used to construct the complete logic, and simulated using the Xcelium Logic Simulator.
2. Synthesis stage: The simulated RTL is converted into a gate-level netlist using the Genus Synthesis Solution.
3. Implementation stage: With the gate-level netlist, the physical layout is designed using the Innovus Implementation System.
4. STA stage: With extracted data, perform timing signoff using the Tempus Timing Solution, and finally generate the GDSII file.

The role of creativity in the RTL design lies in the initial stage, such as how designers conceptualize functionalities, architect the RTL, and focus on functional verification to meet the design specifications and parallelly optimize the design for performance, power, and area. The role of the synthesis is to transfer the RTL design into a gate-level netlist. In this stage, the designers balance the creative intent with the need for optimizations, using the techniques like logic restructuring and technology mapping to improve performance and efficiency. Likewise, creativity plays a crucial role in the placement and routing stage, especially during floor planning. The design blocks are placed strategically on the chip to optimize performance and minimize the area. Similarly, the remaining stages, like timing signoff, involve creatively optimizing the design to meet specified timing constraints using the techniques like gate sizing, buffer insertion, etc. Where timing closure requires a blend of engineering expertise, analytical thinking, and creative problem-solving, so throughout the RTL-to-GDSII process, the designers must combine their technical knowledge with innovative thinking to ensure the chip meets performance targets, making our lives easier today.

As you may know, Cadence provides an RTL-to-GDSII online course that covers the complete flow in detail, including the labs for each stage of the flow. Recently, this course, Cadence RTL-to-GDSII v5.0, has been updated to the latest version 5.0 with new features.

What's New in the Latest RTL-to-GDSII v5.0 Online Course?

The latest version of the Cadence RTL-to-GDSII v5.0 course has been updated with new sections, including how to:

• Place IO pins.
• Choose a suitable buffer to fix hold violations.
• Fix timing violations with detailed steps.

Want to Learn More?

We organize this Cadence RTL-to- GDSII Flow training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Register for the Online Training with the following steps:

1. Log on to cadence.com with your registered Cadence ID and password.
2. Select Learning from the menu > Online Courses.
3. Search for Cadence_RTL-to-GDSII_Flow 5_0 using the search bar.
4. Select the course and click Enroll

And don't forget to obtain your Digital Badge after completing the training!

Related Resources

For more information on Cadence's digital design and signoff products and services, visit the Digital and Signoff Products Release 22.1 page.