Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow.

The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Power efficiency has always been a challenge for ASIC engineers — more so with the escalating size and complexity of the modern digital designs used to build smart devices. As the amount of data increases in tandem with performance enhancement, power requirement becomes daunting, and therefore power vectors become a vital piece of the puzzle to achieve an efficient design. Tools that calculate only the block power consumption or the block activity level do not accurately reflect the true distribution of power inside the block. One of the most critical requirements for accurate gate-level power consumption is the switching activity for the nets in the design. The switching activity of a design refers to how often the different nets change their signal level. Switching information or power vectors can be generated using the gate-level simulation, whose output is then used to estimate the dynamic power consumption of the circuit.

The common questions posed by advanced chip designers when generating activity or vector-based power or IR drop report are:

• Is the activity file meaningful in terms of activity/power consumption? In other words, does it accurately identify those parts of the design that are power-hungry?
• How can a reasonable runtime and memory usage be estimated, given the fact that there are billions of nodes and that the activity file is several ms long?
• How can one determine the functional vectors that cause the highest power consumption?
• How does one ensure that there is enough design coverage?

This is where the Voltus Vector Profiling flow can help. Let’s look at what vector profiling is, how it works, and how it can provide a robust solution to the challenges that ASIC designers are facing.

What is Vector Profiling?

The Vector Profiler flow uses the full vector output of a logic simulator and identifies the windows with maximum activity and power which can then be used to drive dynamic vector-based power analysis. A window is a contiguous subsection of a vector whose length is specified by a time period that is typically user-defined (default 10ns).  The input vector file may be a VCD, FSDB, SHM (from Xelium), or PHY database (from the Palladium emulation platform). Vector Profiler can help localize the section of the activity file that is consuming a lot of power, such as memory writing. Similarly, it identifies the ones that need to be excluded for analysis, such as idle modes that do not consume a lot of power. Voltus supports both fixed windows and variable-sized windows (also known as smart windows). Smart windows profiling is a unique new feature in Voltus where the tool can pick multiple windows of variable size to highlight the peak power or activity within the vector.  The feature allows designers to specify the window type of their choice to be used for current construction and waveform file generation.

How to Run the Vector Profiling Flow?

The following diagram represents the basic steps of the vector profiling flow:

How to Measure the Success of Vector Profiling?

Performing the vector profiling flow is just the first part. To find out whether activity profiling is achieving its goal, you need to analyze the reports. Both ASCII reports and histograms are generated by Voltus for analysis and debugging. The window or step size can be default or user controlled.

The 4 types of vector profiling reports are described below:

• Activity – Reports the maximum activity/toggle windows in the activity file.
• Power – Reports the windows in the activity file with the maximum power consumption.
• Delta Activity – Reports the windows in the activity file with worst da/dt (rate of change of activity).
• Delta Power - Reports the windows in the activity file with worst dp/dt (rate of change of power).

Delta Power and Delta Activity are good indicators of the switching data as they capture the sudden of change of power and activity, indicating the possibility of a high IR drop.

In addition to these reports, design engineers have the option to save a vector profile database that stores the histogram information. These histograms can be read in a Simvision session (the waveform viewer included in Voltus).

The advantage of using histograms in Simvision is that you can immediately load the activity file stimuli to see which events are causing a power jump during the simulation.

What are the Vector Profiling Recommendations?

Now that we’ve run through the vector profiling feature in Voltus, here are some recommendations for seamlessly profiling billions of toggles.

• Does the design have very long simulation vectors? Chances are that it will lead to unwarranted memory, disk space, and runtime. If the worst activity windows of an activity file are identified first, the simulation time can be significantly reduced without compromising on IR hotspots.
• Leverage our solution to combine Vector Profiling and Power Analysis in a single run. The flow makes it easy to identify power-hungry cycles by first running Vector Profiling, and then running the Static and Dynamic power analysis on the worst-case window identified by Vector Profiler.
• Perform dynamic power analysis and vector profiling for multiple windows by using the set_power_analysis_mode -worst_window_count parameter. This parameter can be used when you need to combine dynamic power analysis and vector profiling for multiple worst-case windows in a single run.

Wrap up

The key benefits of using the Vector Profiling flow are twofold: the reduction of analysis time and the accuracy of the solution. The Vector Profiler identifies the high-switching windows at the top level of the design and understands its impact on the power delivery network, delivering much faster average and peak power results. The powerful vector profiling reports give good insight and debug solutions for the various design scenarios. By accounting for the switching of the chips, this Voltus smart solution allows you to accurately identify actual weaknesses in the design based on valid power consumption.

Related Resources

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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