Voltus Voice: 3 Commands You Should Know to Debug Power Using Voltus

Voltus IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Power analysis via power reports is a critical step in chip design to optimize power usage, validate power targets, and make informed design decisions. Correlating the accuracy of these power reports and debugging the power analysis issues are, therefore, crucial tasks for power integrity signoff. Developed to address the complexity of today’s multi-million instance designs, the Voltus power reporting and debugging features allow design engineers to easily identify and mitigate the vulnerabilities related to power consumption. Designers can leverage these features to create power-efficient chips that meet performance requirements while managing power consumption effectively.

Following are some questions that often pop up in their minds when analyzing the power calculation reports:

• Has the tool considered all the inputs and settings provided in the script?
• How much power is consumed at different levels of the design hierarchy, such as blocks, modules, or individual components?
• What is the impact of the different power attributes (for example, toggle_rate, reference clock, transition density, load cap, slew, glitch power, and so on) on the power intent?

Voltus addresses all these concerns and more. Focus on these three commands to uncover potential bugs and boost productivity.

get_power

The goal of this command is to query various power-related properties of design objects like nets, pins, and instances. Using this command, you can retrieve power attributes, such as internal power, switching power, leakage power, total power, and toggle rate. By obtaining such power attributes, designers can estimate whether the chip design meets the specified power targets and adheres to design constraints.

"Instance-Based" Power Debug

The following command returns power-related properties of all the power nets connected to the instance clk_buf_1:

get_power -pg_net all -instances clk_buf_1 -attribute {switching_power internal_power leakage_power}

The following is the sample output:

clk_buf_1 VDD 0.002 0.001 0.000001
clk_buf_1 VDDL 0.0001 0.0001 0.0000001

"Net-Based" Power Debug

The following command returns the specified power attributes for all the nets that match the specified pattern master*:

get_power -nets [get_nets master*] -attribute {switching_power toggle_rate activity_source duty_cycle} -include_unit

The following is the sample output:

masterin[1] 0.001mW 0.2 user_annotated 0.5
masterin[3] 0.003mW 0.1 propagated 0.5
masterin[4] 0.005mW 1 constant 1

report_power

report_power, a must-know command for any Voltus power analysis flow, helps designers to generate multiple power reports. The command allows you to generate a power report for the blocks within the context of the full chip. It reports the global as well as specific instance power, clock network power, clock domain power, and net switching power. The header section of the power report can be used to cross-check and ensure that the correct input files and settings are used for power analysis.

The following is a snippet of the header section:

Design: super_filter
*
* Liberty Libraries used:
* AV_wc_on: ../data/libs/slow.lib_ecsm
* AV_wc_on: ../data/libs/pll.lib
*
* Power Domain used:
* Rail: VDD_ring Voltage: 0.9
* Rail: VDD_column Voltage: 0.9
*
* Parasitic Files used:
* ../design/postRouteOpt_RC_wc_125.spef.gz
*
* DEF Files used:
* ../design/super_filter.def.gz
*
* Power View : AV_wc_on
*
……………………..

report_instance_power

Designers can use the report_instance_power command to generate a text-based report for the specified instance. The command is used to determine how the different components of static power are calculated, enabling you to quickly pinpoint and resolve power issues. You can use the report to debug the power numbers after performing power analysis using report_power.

The following command generated a detailed report of the power components of the instance a1/g8, as shown here:

report_instance_power a1/g8 -file g8.rpt

Instance: a1/g8
Cell: AND2X1
Liberty file: slow_vdd1v2.lib
Internal power: 0.00024141mW
Switching power: 0.00583200mW
Leakage power: 0.00000077mW;
Total power: 0.00607418mW;
Direction Voltage(V) Duty Density Cap(pf) Rise slew(ns) Fall slew(ns) Power(mW) Net Pin
Input 1.08000004 0.25000000 1.750000e+08 0.00325869 0.04000000 0.0800000 0 a1/in2 A
Output 1.08000004 0.12500000 1.250000e+08 0.08000000 1.18739989 1.32619996 0.00583200 out1 Y
Leakage power
When Duty Power
((A) & (B)) 0.125 0.125*1.53e-09
((A) & (!(B))) 0.125 0.125*7.04e-10
Internal power
From To when activity/ns duty energy power(mW) Power Pin
A -> A (1) : 0.175 1 1.655e-16 2.89625e-05 (default)
B -> B (1) : 0.15 1 1.275e-16 1.9125e-05 (default)
B -> Y ((A)) : 0.125 0.3 4.455e-16 5.56875e-05 (default)
A -> Y ((B)) : 0.125 0.7 1.1011e-15 0.000137638 (default)

Power debug of your design can be started early in the design process to minimize the power consumption and meet power targets. By using these commands to retrieve power-related data, you can ensure that the design meets its power requirements in shorter development cycles.

Related Resources

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.