Voltus Voice: Elevate Your Power Signoff Approach Using 3D Vector Profiling

Voltus IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with Cadence's full suite of design implementation and signoff tools to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

The best part of a song sometimes is either its compelling lyric, the tune played on a mesmerizing instrument, or the overall rhythm with a harmonic beat. Although it seems homogeneous, the composer would have spent a disproportionately large amount of time and effort to create that specific element of the song. The meticulous endeavor by the composer on that special element can be compared to how the chip designer carefully spends time identifying the high-power consumption areas that can have a profound impact on the effectiveness and reliability of the SoC. Pinpointing power-hungry windows in an SoC is vital because these areas have a substantial impact on the chip’s overall power profile, thermal behavior, and battery life. They represent the portions of the chip where energy is concentrated and often dictates its overall efficiency.
The previous blog "How to Find Functional Power Vectors that Matter Quickly?" on event-based power analysis primarily delved into discussing how Voltus identifies the worst activity and worst average power cycles in the VCD/FSDB that are then used for detailed dynamic power and IR drop analysis. In contrast, this blog shifts it’s focus on a novel methodology of 3D profiling a vector, based on the time and physical region coordinates. The rationale behind developing a 3D vector profiler is that IR drop violations, especially on advanced nodes, are caused by localized high power consumption in different regions of the chip rather than total peak power of the chip. Since high power in these regions may vary across time, there is a possibility that while running the chip for merely one continual brief period, we may overlook the major hotspots of the design.

What Is 3D Vector Profiling?

With power signoff using Voltus 3D vector profiling, designers can now use the tile dimension approach for power density calculation. Under this framework, the tool analyses the core regions of a design with high-power density that could, in turn, produce high switching current and IR drop. In this flow, the tool uniformly partitions the design into a two-dimensional array of equally sized tiles and computes power density of each physical tile at every time step. The Voltus power engine then selects and combines the worst power intervals corresponding to multiple but distinctive fractions (tiles) of design for transient current and rail signoff.

This proposed solution addresses the most common limitations of the IC Power Signoff tools:

• Amplified Design Coverage: considers the maximum number of unique tiles ensuring coverage of most areas of the design exhibiting high power density.
• Unique Time Intervals: performs power analysis at a definite continuous time interval stretch, picking the different windows showing high power.

Profiling Methodology

We know that the distribution of power density within an SoC will inherently exhibit arbitrariness regarding its physical allocation and vector duration. As shown in the following diagram, the design is first dissected into smaller tiles, where the tiles exhibit varying power levels at different timestamps.

Figure 1. Power density concentration across different regions of design at different time stamps

Here, the tile in {30-40ns} duration is showing maximum power followed by the tile in {0-10ns} duration. In the next step, the tool will combine the multiple worst-case window intervals based on a user-defined option to ensure better coverage of the design. If you choose to combine the top 2 windows in this scenario, the tool will select the tiles in {0-10ns} and {30-40ns} duration and concatenate the windows for current construction. In case the selected window intervals are not consecutive, a small settling buffer of a few picoseconds could be added in between the intervals to maintain the linearity of toggles and current within the window. User can select how many distinct windows they want to combine to create a synthesized vector that can be used for transient rail signoff.

Figure 2. Worst Windows Selected for Dynamic Power Analysis

Power Reporting with 3D Vector Profiling

The event-based flow reports all the tile-based information used by the tool, which can then be accessed for debugging purposes. The power report comprises of the following sections:

• Tile Details - includes the information related to the tile dimensions, count, location, and ID.
• Worst Tile Profile for Each Step - gives a list of the tiles with the maximum power density for each time step.
• Worst Time Stamp Profile for Each Tile - reports the maximum power density of each tile for the total duration.
• Intervals Covering Unique Tiles Having Worst Power Density - reports the unique tiles having the maximum power density with exclusive time intervals.
• Detailed Tile Profile for Each Step - presents the internal, switching, leakage, glitch and total power for each tile at each time step.

Figure 3. Tile based Power Reporting Categories

Key Takeaways

The 3D vector profiling flow ensures that all critical areas and scenarios are methodically covered. We’ll observe a significant upsurge in IR drop when compared with the default flow, where power and rail analysis is performed on the total peak power or activity window intervals without any selection for localized peak power density. This technique will help designers discover the IR drop hotspots in the design and make informed decisions about power management and optimization, reducing the risk of late-stage design revisions.

So, why don’t you give this power technique a shot at your microchip and see if it accurately captures the hotspots the way your favorite song captured your heart?

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About Voltus Voice

“Voltus Voice” showcases our product capabilities and features and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.