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Voltus IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with Cadence's full suite of design implementation and signoff tools to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.
In this second installment of our blog series "Multi-Chiplet Marvels," we continue to journey through the fascinating realm of three-dimensional integrated circuit (3D-IC) technology, where boundaries are pushed and possibilities are redefined. 3D-IC involves stacking multiple transistors or metal/via layers to achieve higher integration, reducing interconnect lengths, improving performance, and packing more functionality into much smaller form factors. The increasing interest and adoption of advanced packaging methods, often referred to as "More than Moore," have prompted many leading-edge companies to leverage these technologies to differentiate from their competitors. Within this landscape, 3D-IC holds great potential in areas like artificial intelligence (AI) or machine learning (ML), high-performance computing like weather modelling and aerospace technology. Overall, 3D-IC offers many advantages, including enhanced data transfer speed, expanded storage capacity, design flexibility, and reduced power consumption.
3D-IC Power and IR Integrity Challenges
In advanced 3D-IC technologies like Wafer-on-Wafer (WoW), Integrated Fanout (InFO), Chip-on-Wafer-on-Substrate (CoWoS), and System-on-Integrated-Chips (SoIC) structures, the power integrity analysis and signoff solutions have become increasingly intricate and time-consuming. These technologies involve integration of heterogenous chips onto a single chip stack for the subsequent packaging process. This translates to a demand for high-performance and low power consumption in large heterogeneous designs, encompassing millions of connection bumps and several hundred million instances.
To address this need for chip-package-board total power signoff co-analysis, Voltus 3D-IC provides a comprehensive solution that enables concurrent static/dynamic Power/IR/EM analysis across die and silicon interposers while reducing the run time. This integrated solution allows users to specify the net- and pin-based details for the package, die model, and stacked dies, facilitating co-simulation and verifying the overall power grid logical connectivity and IR/EM performance of the complete system.
A Unified Approach for Integration of Heterogenous Chips: Voltus Multi-Die Analysis
In terms of die-level and system-level analysis, Voltus Interfaces with Innovus and XtractIM to implement and analyze any type of stacked die system for a variety of packaging styles (2.5D or 3D).
The Innovus environment identifies the bump locations and generates a bump mapping file for die-level designs. Voltus works with XtractIM to extract the package netlist for the die-to-package connection. Thereafter, Voltus considers these inputs along with the LEF/DEF design, die models, and PG domain information to enable power and IR drop analysis in the multi-die mode.
Our Analysis Revelation: 3D-IC Reporting Blitz and SuperGUI
When it comes to the IR signoff review of single die analysis, the report and GUI presentation are straightforward for designers. In contrast, creating sign-off reports for multi-die analysis is exceedingly complex due to the challenges posed by the vertical stacking and design scale. Determining whether an IR violation originates from the PG route, die-to-die connection, die-to-package connection, or a single die bump allocation becomes a daunting task.
The Voltus 3D-IC signoff flow considers various factors, such as the current flow through different dies, voltage drop of different types of bumps, connectivity check, PG short check, electrostatic discharge (ESD), electromigration, and more. Over time, the reporting system has evolved to provide designers with improved visibility and superior debugging capabilities, allowing them to better understand the design at the architecture level.
The introduction of SuperGUI in Voltus represents a new era. While the previous Distributed GUI utility was limited to single-die analysis, SuperGUI introduces a multi-plot view that displays results from each die concurrently. This enables rapid visualization of the Least-Resistance Path (RLRP) in each die or across different dies. Special features, such as flip, rotation, mirroring, and even XML-based synchronization demonstration, are available to analyze the design in more depth and in various dimensions.
The Last Words...
While the initial allure of 3D-IC technology is undeniable, it is important to acknowledge that the increased design density also brings forth challenges such as thermal issues, crosstalk, and power and IR violations. To combat these issues and prevent costly and time-consuming re-spins, Voltus 3D-IC signoff offers an effective solution. This integrated solution ensures seamless design implementation while its simulation solver has the capacity to handle extremely large designs. Furthermore, Voltus extends its functionality to cater specifically to 3D-IC requirements, including die model, Extreme Modeling (XM), and ESD protection. The intuitive 3D-IC reporting and GUI capabilities of Voltus act as a formidable weapon to facilitate robust reporting and visualization, thus letting us dive confidently into the era of 3D-IC technology.
For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.
“Voltus Voice” showcases our product capabilities and features and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.