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Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design
Latest blogs

Hands Up, Anyone Believe That Toyota's Problems Are All Physical?

In the past number of weeks/months we have all seen how Toyota has struggled to manage…

• 2 min read
toyota , Digital Implementation , BMW , microprocessor , verification

EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D

Every April the leading edge of the leading edge of semiconductor industry meet…

• 3 min read
DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , stacked die , flip chip , PoP

IR Drop Analysis: It's Not Really Necessary, Is It?

I was recently asked by an engineering manager if running IR drop analysis was really…

• 2 min read
VDD , VDD I/O , Digital Implementation , IR drop , EM Failures

My DATE With 3DIC Technology

This year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden…

• 3 min read
DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , stacked die , flip chip , PoP

Signoff-Driven Implementation = Consistent and Convergent = Predictable and Effi…

Digital designs are reaching 10's of millions of instances, which makes efficiency…

• 2 min read
timing system , dynamic rail analysis , Static timing analysis , Early Rail Analysis , Multi-Core and Parallel rocessing , Statistical , Extraction , Signoff Analysis , timing constraints , SI analysis , noise analysis , OCV , Signal Integrity , Digital Implementation , Timing analysis , Power Analysis , signoff , timing convergence

Encounter How To: Writing To/Reading From a File With TCL

A couple weeks ago, there was a good thread in the Digital Implementation Forums…

• 2 min read
EDI system , encounter digital implementation system , Digital Implementation , Closure , Foundation Flow Design , scripting , tcl

User Review of The Encounter Foundation Flow

This is a guest post from John McGehee. John is an independent consultant in Silicon…

• 4 min read
Foundation Flow , Encounter Digital Implementation System 9.1 , scripting , Encounter Digital Implementation System 8.1

Three Reasons to Move to EDI System 9.1

We recently announced the 9.1 version of the Encounter Digital Implementation System…

• 1 min read
Foundation Flow Design Closure , Encounter Digital Implementation System 9.1 , Digital Implementation , EDI system Encounter Digital Implementation System

Encounter Screencast: Editing Wires More Quickly With Bindkeys

The Encounter Digital Implementation System offers interactive wire editing capabilities…

• 1 min read
Wire Editor , encounter digital implementation system , Digital Implementation , bindkeys

Sometimes It's The Little Things: Working With Square Brackets in Encounter

Good news! A long-standing source of irritation for Encounter users has been addressed…

• 1 min read
Ease of Use , Encounter Digital Implementation System 8.1

Design Signoff Begins In Implementation

As an ex-design engineer now working in EDA, I am often privileged to see advanced…

• 1 min read
dynamic rail analysis , Static timing analysis , SI , Early Rail Analysis , ets , cadence , EDI system , Signoff Analysis , encounter digital implementation system , EPS , Signal Integrity , Cadence Encounter Power System , Digital Implementation , crosstalk , CeltIC , tapeout , design closure , encounter power system , Encounter Timing System , timing convergence , "SoC-Encounter" , blog

Trying to Figure Out Social Media? Ron Ploof Says "Read This First"

Left to Right: Ron Ploof, Bob Dwyer Photo Credit: brillianthue "As a New Media evangelist…

• 6 min read
Facebook Twitter , New Media , EDA , Social Media , Ron Ploof

Encounter How-To: Selecting Objects By Pointer With dbGet And dbSelectObj

I just got back from a trip to California where I met with a couple of customers…

• 3 min read
database access , dbGet , Digital Implementation , Encounter Digital Implementation

Find, Fix And Learn With Cadence Online Support

We recently rolled out a new online support mechanism that replaces Sourcelink called…

• 1 min read
Sourcelink , Cadence Online Support , Digital Implementation

Cadence and Very Cool Stuff

One of the very cool things about my job is that I get to see all kinds of new stuff…

• 3 min read
PSO , innovation , MSV , Digital Implementation , FED

Encounter How-To: Write Text to The Log File With "Puts"

Here's a simple but useful tip that shows how to write to the log file using the…

• 1 min read
EDI system , Digital Implementation , Encounter Digital Implementation , tcl

How To: Purge Interactive Constraints in MMMC Mode

These tips are applicable to the Encounter Digital Implementation System . Back in…

• 3 min read
timing constraints , Digital Implementation , mmmc , Encounter Digital Implementation System 8.1 , tcl

Leakage Power and National Security

I read an interesting article recently on EDN regarding a new way to determine cryptographic…

• 1 min read
Palladium DPA , leakage , Digital Implementation , power

Running Low on Power or Receiving Mixed Signals? Talk to the Expert Users

Everytime my wife and I are looking to buy a big item, we do our research by reading…

• 1 min read
Mixed-Signal , Logic Design , Digital Implementation , mixed signal , verification

Lost and Found: Missing Filler Cells, Power Vias, and Highlighted Objects

Have you ever gotten to signoff DRC and found that there was a small area where a…

• 2 min read
power vias , filler cells , highlighted objects , checkFiller , 8.1 , Digital Implementation , verifyPowerVia , "SoC-Encounter" , F9

Co-Design - Its Not Just an Exercise in Excel Any More - Learn Why at the Aug. 26…

Co-Design … some are trying to do it with spreadsheets … everyone is talking about…

• 1 min read
SoC-Encounter , Cadence SiP , Co-Design , Digital Implementation , FlipChip

Useful dbGet One-Liners

We've gotten some good feedback about posts in this forum relating to dbGet and dbSet…

• 2 min read
dbGet , dbSet , Digital Implementation

5 Fascinating People I Met at the 2009 Design Automation Conference

As much as the Design Automation Conference (DAC) is about demonstrating solution…

• 5 min read
DAC , Digital Implementation

Reducing Risk and Improving Productivity with the Cadence InCyte Chip Estimator and…

I'm looking forward to heading out to San Francisco next week for the 46th Design…

• 1 min read
DAC , Digital Implementation , Cadence InCyte Chip Estimator , Encounter Digital Implementation System 8.1

How To: Create a Self-Contained Testcase in Encounter

In the course of performing design work in Encounter, it frequently becomes desireable…

• 2 min read
Digital Implementation forums , How To , testcase , Encounter Digital Implementation System 8.1

Using A Dual Flop Methodology for Dynamic Power Savings

Imagine this scenario: Your chip is a low power design. You’ve used everything in…

• 1 min read
Low Power , dual flop , Digital Implementation

Flow? What Flow?

For EDA software, it seems that it takes just as much effort to develop a methodology…

• 1 min read
Foundation Flow , EDI system , encounter digital implementation system , Digital Implementation , design closure

Cadence: Committed to DFM

On June 10, Cadence issued a press release that mentioned “…decreasing the level…

• 1 min read
Advanced Node , Mixed-Signal , encounter , Virtuoso , Manufacturability sign-off , Digital Implementation , DFM
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