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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Welcome to Richard Goering

Let me be among the first in the Cadence "blogger corps" to welcome Richard Goering…

• less than a min read
Industry Insights , Functional Verification , EDA

Software Verification or Validation With ISX?

[Please welcome Markus Winterholer to the Team ESL blog. Markus is one of the founding…

• 2 min read
validation , embedded world conference , System Design and Verification , ISX , ARM , verification

DVCon '09 SaaS Panel Thoughts, Part 3

In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS"…

• 5 min read
SaaS , Functional Verification , Harry The ASIC Guy , DVcon , Xuropa

Is Software Engineering Engineering? You Decide!

Last night when I was waiting for my daughter to finish orchestra rehearsal (she…

• 3 min read
System Design and Verification , failure tolerance , software engineering , design metrics

Moving Low Power Chip Design up to the System Level

Anybody watching Cadence these past couple years has probably noticed how we're pretty…

• 1 min read
System Design and Verification , Palladium , incyte , C-to-Silicon Compiler

Generation Action: Constraints From Above

[Welcome guest blogger Reuven Naveh of Specman R&D] What is the “constraints from…

• 6 min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Tracing TLM 2.0 Activity In An ESL Design – Part I

Many design teams that use SystemC are in various stages of evaluating TLM 2.0 –…

• 6 min read
TLM , System Design and Verification , TLM 2.0 , SystemC analysis , George Frazier , sctlmrecord , ESL

Making the Right Decisions *Before* You Start Your Project

Seems logical, but unfortunately, I run into customers today that grumble about their…

• 3 min read
InCyte IP , chipestimate , System Design and Verification , chip estimation

Connecting OVM Testbench and SystemC TLM2 IP

1. Introduction With TLM2 enabling more sophisticated SystemC IP interoperability…

• 9 min read
TLM2 IP , System Design and Verification , OVM , SystemC , testbench

C-to-Silicon Compiler Is The Only ESL Tool With ECO Capabilities

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to other…

• 1 min read
ECO , CTOS , RTL , System Design and Verification , C-to-Silicon , ESL

IMPORT Guidelines For e, Part 1

[Team Specman welcomes AE Manager Avi Behar as our newest guest blogger] Hi, my name…

• 4 min read
IntelliGen , Specman , Functional Verification , Avi Behar , OVM e , Register Package , e , OVM-e , specman elite , Aspect Oriented Programming , eRM , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

DVCon '09 SaaS Panel Thoughts, Part 2

In my last post on the DVCon 2009 panel on Software As A Service , or " SaaS " as…

• 3 min read
security , SaaS , Functional Verification , Harry The ASIC Guy , DVcon

New eDocs Makes Documenting Fun!

Documentation. This single word tends to sends shivers up the spine of many an engineer…

• 3 min read
Specman , Functional Verification , e , specman elite , OOP , hvl , AOP , verification

Tech Tip: Determining When a Sequence Has Finished

Imagine the complex scenario whereby you start the *same* sequence on multiple sub…

• 1 min read
IEEE 1647 , Specman , Functional Verification , OVM e , e , Aspect Oriented Programming , eRM , AOP

Users Report on OVM in a Multi-Language World: Results From DVCon

The OVM user reports from Xilinx, SiRF, and ST at the DVCon luncheon were real engineer…

• 1 min read
SystemVerilog , OVM , OVM e , OVM SV , e , DVcon , SystemC , OVM SC

DVCon '09 SaaS Panel Thoughts, Part 1

[Preface / Disclaimer: I haven't yet had the pleasure of working closely with Cadence…

• 1 min read
SaaS , metric driven verification (MDV) , Functional Verification , Coverage-Driven Verification , CDV , Harry The ASIC Guy , DVcon , coverage driven verification (CDV)

SystemC Save and Restore Part 2 - Advanced Usage

In my last post I discussed how to use save / restore in the Cadence Incisive Simulator…

• 3 min read
System Design and Verification , embedded software , Incisive , virual platform , virtual prototype , George Frazier , SystemC , Hardware/software co-verification , ESL

OVM-e Sequence API Brings Increased Flexibility

Specman 8.2s2 adds new Application Programming Interface (API) methods to sequence…

• 6 min read
Specman , Functional Verification , API , OVM , e , eRM

Quick Tip: Searching for Special Characters in Cadence Help

[Team Specman welcomes back the Technical Publications Team to guest blog] A logical…

• less than a min read
Tech Pubs , Functional Verification , Cadence Help

Exploring the Virtual Platform Part 5

Welcome to part 5 of the Exploring the Virtual Platform series. This is probably…

• 5 min read
busy box , virtual platform , System Design and Verification , linux

Five Common Pitfalls For Conference Panels

Panels are some of the most popular sessions at many technical conferences. Getting…

• 2 min read

Experiment With Cadence's MIPI VIP Live in The Xuropa Online Lab

At risk of being lost in all the excitement of DVCon 2009 last week , my colleagues…

• 1 min read
funtional verification , Functional Verification , Cadence VIP portfolio , VIP , MIPI , Xuropa

Summary of a Really Busy DVCon Week

Joe Hupcey has done his usual fine job of documenting DVCon ( day 1 , day 2 , day…

• 1 min read
Functional Verification , OVM , DVcon , SystemC

OVM Multi-language Libraries – A Closer Look

Originally architected for multiple languages, the OVM is now available for all…

• 2 min read
SystemVerilog , OVM , VIP , OVM e , OVM SV , e , multi-language , SystemC , OVM SC , AOP

DVCon 2009 - Day 3

Today I was able to cover a paper on "OVM-based Methodology for Low Power Designs…

• less than a min read
funtional verification , verification strategy , Functional Verification , Formal Analysis , Testbench simulation , DVcon

ESL Design - SystemC TLM2 IP Authoring: A Practical Experiment

Introduction ESL Virtual Platforms (systems or sub-systems) require heterogeneous…

• 8 min read
IP-XACT , System Design and Verification , Incisive , virtual prototype , Spirit , SystemC , osci registers , systemrdl

DVCon 2009 - Day 2

Here are some pictures from DVCon 2009 Day 2, focusing on the OVM Case Studies lunch…

• less than a min read
SaaS , Verification methodology , OVM , OVM-e , DVcon

Using TLM Verification To Reduce RTL Verification

SystemC is the most common language used for modeling transaction level (TLM) behavior…

• 1 min read
TLM , Functional Verification , RTL , automation , planning and management , testbench
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