Featured

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

Streamline PCIe 6.0 Switch Design with Effective Verification Strategies

The demand for PCIe 6.0 switches has surged due to the exponential growth in global…

• 4 min read
non flit mode , Functional Verification , switch , VIP , switch performance , PCIe 6.0 , flit mode

Training Insights: Introducing the C++ Course for All Your C++ Learning Needs!

This course, "C++ Fundamentals for Design and Verification v24.03" provides an introduction…

• 2 min read
C++ , verification

USB4 Version 2.0 – Low Power with Gen4 Link

USB4 Version 2.0 specification was released by the USB Promoter Group two years back…

• 3 min read
USB4 VIP , USB4v2 , usb4

Cooking Up Better Performance for Arm-Based SoCs

With increasing complexity, ascertaining performance in Arm-based SoCs design has…

• 3 min read
featured , chiplets , Arm-based SoC , cadencelive , ARM , Arm Performance cookbook

Exploring the Security Framework of RISC-V Architecture in Modern SoCs

Introduction to System on Chip (SoC) Security In the rapidly evolving world of…

• 2 min read
security , PMP , risc-v , cadence , SoC , mediatek

Integrating Coherent RISC-V SoCs: Advanced Solutions with Perspec

In the rapidly evolving Systems on Chips (SoCs) landscape, the need for more efficient…

• 2 min read
SoC verification , risc-v , Perspec , RISC , coherency

RISC-V: Democratizing Innovation in CPU Design

RISC-V has emerged as a groundbreaking force in the semiconductor industry, fundamentally…

• 3 min read

Cadence Memory Models - The Gold Standard

In today’s world, we’ve been seeing an unprecedented rise in the use of “data” with…

• 4 min read
Verification IP , Functional Verification , Cadence VIP portfolio , VIP , memory models

Testing and Training HBM (High Bandwidth Memory) DRAM Using IEEE 1500

HBM is a JEDEC (Joint Electron Device Engineering Council) standard-defined DRAM…

• 3 min read
Verification IP , uvm , Functional Verification , Cadence VIP portfolio , System Design and Verification , VIP , Memory Model Portfolio , memory models , verification

Serial NAND Flash: New Octal SPI Dual Data Rate Capabilities

Serial NAND Flash NAND Flash has been in a constant battle to prove its competitive…

• 5 min read
Verification IP , Functional Verification , NAND flash controller , serial flash , VIP , octal spi , flash memory , Memory Model , MMAV

Riding the AI Wave Using HBM (High Bandwidth Memory)

The ever-increasing innovations in artificial intelligence (AI) are revolutionizing…

• 3 min read
Verification IP , uvm , Functional Verification , Cadence VIP portfolio , System Design and Verification , VIP , Memory Model Portfolio , memory models , verification

LPDDR5X Opening New Markets for Low-Power DRAMs

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor…

• 4 min read
Verification IP , Low Power DRAMs , Memory , LPDDR Market , LPDDR , VIP , JEDEC , lpddr5 , lpddr5x , verification

Cadence Introduces the Industry’s First GDDR7 Verification Solution

GDDR7 Introduction In February 2024, JEDEC announced the successor to GDDR6 with…

• 3 min read
Verification IP , Functional Verification , Cadence VIP portfolio , memory models , GDDR7 , System Design and Verification

Flash Memory Demystified: Nor Flash Vs. Nand Flash

In the world of flash memory, two primary types dominate the market: NOR flash and…

• 4 min read

Navigating the Complexity of Address Translation Verification in PCI Express 6.0

The Address Translation Service (ATS) is a crucial process in the Peripheral Component…

• 5 min read
Verification IP , Functional Verification , VIP , PCIe

Beyond Gigabit: Navigating the Terrain of 1600G Ethernet Networks

In the ever-evolving landscape of networking technologies, the arrival of 1600G Ethernet…

• 2 min read
Verification IP , Ethernet VIP , Functional Verification , VIP , Ethernet standards , Ethernet , Ethernet PHYs , ethernet 1600G

Verisium SimAI: Machine Learning for Efficient Design Verification

Are you tired of spending hours on tedious tasks like debugging and coverage closure…

• less than a min read
ml , coverage , Functional Verification , bugs , verisium , DV , machine learning , SimAI , xcelium , AI

Pre-Silicon Software Execution and Performance Validation – A Case Study

In a persistent trend, shrinking IC geometries and higher levels of integration are…

• 12 min read
prototyping , Protium , Emulation , FPGA

Lightmatter Matters - Photonics-Based Verification with Xcelium Mixed-Signal App

Traditionally, analog mixed signal (AMS) verification works by utilizing a connection…

• 3 min read
lightmatter , mixed signal , xcelium , bind-to-spice

Training Insights: Reaching Your Verification Closure Using Verisium Manager

For a while now, Cadence has led the Verification Planning and Management (VPM) domain…

• 2 min read
Functional Verification , System Design and Verification , verisium , Verisium Manager , vManager , verification

Verifying SoC BootROM Using Standard Verification Techniques

BootROM is still found in system-on-chip (SoC) designs, especially where security…

• 4 min read
ROM , coverage , BootROM , verification

Training Insights – A Brand New Free Online Course on UCIe VIP Introduction

The Cadence VIP portfolio is used to provide various standard protocol VIPs for testing…

• 3 min read
digital badge , live training , blended training , ucie , online_training , Verification IP , VIP , Training Insights

Weak Verification Plans Lead to Project Disarray - How to Fix That

The purpose of the verification plan, or vplan as we call it, is to capture all the…

• 2 min read
coverage , quality , debug , vPlan , Verisium Debug , vManager

The Year That Was: Training Insights Training Bytes Blog and Video Highlights from…

As we welcome 2024 now we will not miss to look back at our most-viewed blogs of…

• 2 min read
digital badge , online_training , System Design and Verification , Protium , blended_training , training , webinar , training bytes , Verisium Debug

What Is Viral in CXL 3.0?

Introduction to CXL 3.0 CXL 3.0 is an open-standard interconnect technology that…

• 3 min read
CXL , Verification IP , viral , Functional Verification

Understanding Embedded USB2 (eUSB2) and its usage

The need for higher processing power and lower power consumption are driving processors…

• 2 min read
VIP , USB , eUSB2

Unraveling PCIe 6.0 Loopback and Digital Near-End Loopback Feature

PCIe spec has given a specific LTSSM state named Loopback , which is intended for…

• 2 min read
PHY , NELB , Loopback , Gen6 , PCIe 6.0

DisplayPort 2.1 vs DisplayPort 1.4: A Detailed Comparison of Key Features

DisplayPort is a digital display interface developed by the Video Electronics Standards…

• 2 min read
Verification IP , Functional Verification , DisplayPort
Blog - Title