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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

IntelliGen Moving Into The Spotlight With Pgen Deprecation

Specman's new Aspect Oriented Generation Engine, IntelliGen, has now been in service…

• 1 min read
IntelliGen , Specman , VIP , EDA , e , Funcional Verification , team specman , specman elite , Aspect Oriented Programming , CMS , Incisive Enterprise Simulator (IES) , AOP , IES-XL

DAC360: Photo blog of DAC 2010 in Anaheim, CA

Click here or on the image below to go to the annotated photo blog of DAC 2010. Images…

• less than a min read
DAC , Specman , TLM , Functional Verification , IBM , OVM , EDA360 , TSMC , Palladium XP , Mike Stellfox , Denali , iPad , AMIQ , Twitter , XJTAG , IEV , Incisive Enterprise Simulator (IES) , Accellera VIP TSC , IFV , IES-XL

DAC Cabbie Taught Me All I Need to Know About Verification

Confidence from competence. Measurement through metrics. Sell without selling. These…

• 4 min read
SystemVerilog , DAC , uvm , ABV , OVM , EDA360 , Register Package , Incisive , Funcional Verification , AMIQ , Twitter , MDV , Accellera VIP TSC , IES , VMM

What's The Best Way To Reduce SoC Development Costs?

Before I got started with my DAC 2010 customer meetings on Monday morning, I stopped…

• 2 min read
TLM2 , virtual platforms , virtual prototypes , SystemC , DAC 2010

Hit The Road - DAC!

OK, now that the Design Automation Conference (DAC) seems to be rotating among San…

• 1 min read
DAC , uvm , Functional Verification , OVM

Snapshots From Day 0 of DAC 2010

Below are some snapshots of some "day 0" events, and last minute DAC preparations…

• less than a min read
DAC , uvm , OVM , Palladium XP

Advanced Option Brings New Features to Specman/e Users

Great news for Specmaniacs -- a new Specman Advanced Option is being announced at…

• 1 min read
SystemVerilog , DAC , Specman , Functional Verification , Multi-Core , e , team specman , specman elite , Incisive Enterprise Simulator (IES) , IES-XL

A New Toy for UVM Geeks

Wasn't it great when you were a kid at Christmas, and you got all those new toys…

• 1 min read
SystemVerilog , methodology , Verification methodology , metric driven verification (MDV) , Functional Verification , Incisive , MDV

Cadence Contributes ESL Methodology To TSMC Reference Flow 11

The EDA360 industry vision document shows how growing complexity and application…

• 3 min read
ECO , OIP , C to Silicon , TSMC , system , ESL , verification

Accelerating Metric-Driven Verification With “Hotswap” on Verification Computing…

For a while now, Cadence has been providing leading verification solutions and methodologies…

• 1 min read
emulator , DAC , Acceleration , Palladium , hotswap , Emulation , hot swap , metric , metric-driven verification , MDV

Specman, e, and EDA360

The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward…

• 5 min read
SystemVerilog , DAC , AMS , uvm , Specman , IP , HW/SW , methodology , CDNLive , metric driven verification (MDV) , Functional Verification , VIP , EDA360 , Mixed Signal Verification , Multi-domain verification: HW/SW co-verification , Incisive , e , OVM-e , ISX (Incisive Software Extensions) , ClubT , Aspect Oriented Programming , SystemC , ISX , MDV , Incisive Enterprise Simulator (IES) , VHDL , ESL , AOP , Matlab , IES-XL , Trailblazer

India Takes The Lead By Hosting The First Two “ClubTs” in 2010

Specman/ e users in India were very excited to see the first two ClubT events hosted…

• 4 min read
IntelliGen , Specman , Functional Verification , validation , e , team specman , ClubT , AOP , IES-XL

System Development – What To See At DAC 2010

The EDA360 vision paper specifies key System Realization challenges. Embedded software…

• 6 min read
DAC , cadence , ITRI , system realization , OSCI , Calypto , TSMC , Gary Smith , Imperas , SystemC , ARM , wind river , HLS , DAC 2010

Bloggers and Journalists and Gadflies, Oh My!

There has been quite a bit of discussion out in the blogosphere about the similarities…

• 3 min read
DAC , Functional Verification , EDA , Blogging , blogs

EDA360 And The "Paperback Computer"

Have you ever heard an assertion that's so intriguing and farsighted that it sticks…

• 7 min read
events , DAC , IP , paperback computer , innovation , metric driven verification (MDV) , Functional Verification , Advanced Node , EDA360 , Verification IP modeling , EDAC

Making an EDA360 System Realization Investment Through Standards Support

Cadence is a sponsor of the Open SystemC Initiative (OSCI) standards organization…

• less than a min read
TLM , C-to-Silcon , OSCI , ESL

C-to-Silicon Compiler 10.1 - Ease Of Use And RTL QoR

In the continuing effort to make high-level synthesis more viable to mainstream RTL…

• 1 min read
CTOS , TLM , C-to-Silicon , Synthesis , HLS

TLM 2.0 As Part Of The EDA360 Vision

Ann Steffora Mutschler recently covered in her blog the progress the industry has…

• 1 min read
TLM , virtual platform , TLM 2.0 , EDA360 , virtual prototype , SystemC , Synthesis , System Design and Verification

EDA360 Is More Than Design IP Plus Software Drivers

I checked my Linked-In messages the other day and saw a survey by Girish Patil with…

• 2 min read
IP , Functional Verification , Virtual Chips , Phoenix , inSilicon , VIP , EDA360 , Sand

The Future of OVM, VMM, and UVM

In my last blog , I took a look back at the history of how we got to the first delivery…

• 3 min read
SystemVerilog , uvm , methodology , Functional Verification , Open Verification Methodology , OVM , VIP , Accellera , Accellera VIP TSC , VMM

Tech TIP: Incisive Formal GUI Updates - Making It Easier

The Incisive Formal GUI has had some recent changes made to it. You asked for the…

• less than a min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

UVM World Community Site Now Available!

Yesterday morning, the verification world was buzzing with the first release of the…

• 1 min read
uvm , Verification methodology , Functional Verification , OVM , VIP , Accellera VIP TSC

UVM - 10 Years in the Making ...

In case you the missed the news today, the Accellera VIP TSC released the first version…

• 3 min read
SystemVerilog , uvm , Specman , OVM ML , Functional Verification , OVM , OVM e , Coverage-Driven Verification , CDV , vr_ad , OVM SV , e , OVM-e , Accellera , coverage driven verification (CDV) , eRM , Accellera VIP TSC , OVMWorld

Initial Release of the UVM Now Available!

As Richard Goering just reported , the Accellera VIP Technical Subcommittee (TSC…

• 2 min read
uvm , Verification methodology , OVM , VIP , Accellera VIP TSC

EDA360: Cool People Creating Cool Stuff

Now that we have had some time to reflect on the meaning of EDA360 , it occurred…

• 4 min read
EDA360 , Systemm Design and Verification , OpenStreetMap , Embedded Linux , Embedded Software Engineer

Inside Cadence: Training for EDA360

Over the past few weeks all of Cadence's Verification and Systems Solutions Applications…

• 5 min read
Specman , TLM , OVM ML , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , OVM , VIP , OVM e , CtoSilocon , OVM SV , e , Enterprise Manager , Palladium XP , MDV , IEV , Incisive Enterprise Simulator (IES) , IFV , IES-XL

FMCAD Call for Papers Extended to May 12

Team Verify would like to inform you about the final call for papers for FMCAD 2010…

• 7 min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

Informative Tweets on WHEN Inheritance

Earlier today a lively and very instructive thread on the relative virtues of WHEN…

• 3 min read
SystemVerilog , when sub-typing , tweeting , Specman , Functional Verification , when inheritance , OVM , OVM e , OVM SV , e , Twitter , AOP , IES-XL
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