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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Must Have Advanced Verification to Achieve Software Signoff

In a recent blog on EDA Graffiti, Paul McClellan he talks about Software Signoff…

• 2 min read
EDA Graffiti , System Design and Verification , embedded isx , software signoff

Specman 9.2 Preview: A Fresh Profile on the Profiler

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to…

• 2 min read
performance , Specman , Functional Verification , e , team specman , IES-XL

Twitter-like Growth For Verification's Trailblazers? (a/k/a A Trailblazer hat tip…

I'm not proud to admit that I reacted with envy to the news that Twitter just received…

• 2 min read
events , Specman , CDNLive , metric driven verification (MDV) , Functional Verification , IBM , VIP , MDV techtorial , DVClub , Enterprise Manager , Enterprise Planner , team specman , DVcon , Twitter , ARM , MDV , verification , Trailblazer

What's the New CMO Mean For Cadence and System Design and Verification?

If you track Cadence stock or other EDA leadership news you undoubtedly know we've…

• 1 min read
ASIC , TLM , System Design and Verification , John Bruggeman , software , embedded , FPGA

Upcoming ARM Techcon3 or is it Techcon Cubed?

The annual ARM Developers' Conference has been renamed ARM techcon3 , or maybe it…

• less than a min read
techon3 , Cypress , ARM , ESL , System Design and Verification

Specman-Matlab Package Update

[Preface: we interrupt the Specman 9.2 Preview series to notify you of an update…

• 3 min read
Specman , Functional Verification , C , e , Incisive Enterprise Simulator (IES) , ESL , Matlab , IES-XL

Back to School and Back to the Embedded Software Challenge

The kids have a week of school in the rear view mirror and it's time to get back…

• 3 min read
DAC , System Design and Verification , virual platform

Incisive Enterprise Simulator: Low-Power Verification at Warp Speed

Since your circuit always runs at low-power, your verification should too. To get…

• 2 min read
funtional verification , CPF , Low-Power , Incisive , IES

Requirements for a Student Version of Specman/IES-XL?

Allow me to interrupt my blogging on MarCom and DAC to pose a question inspired by…

• 1 min read
SystemVerilog , Specman , Functional Verification , student version , Incisive , e , SystemC , Incisive Enterprise Simulator (IES) , IES-XL

Specman 9.2 Preview: Shortened “When Subtype” Declarations

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to…

• 2 min read
Specman , Functional Verification , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , AOP , IES-XL

Wedding at DAC '09: CDNS+IBM's Enterprise Verification Management Solution

Does the union of verification automation and IT+source code management tools get…

• less than a min read
DAC , Tivoli , metric driven verification (MDV) , Functional Verification , IBM , Enterprise Manager , Enterprise Planner , MDV , Rational , Incisive Enterprise Simulator (IES) , IES-XL

Functional Verification and EDA "Startups"

A few weeks before DAC, I started working on a blog post about the number of small…

• 1 min read
DAC , Verification methodology , Functional Verification , Open Verification Methodology , OVM , System Verification , verification

Comment Direct From XJTAG, Ltd.

Simon Payne, the CEO of XJTAG, has responded to my invitation to comment on their…

• 2 min read
DAC , Functional Verification , XJTAG

Specman 9.2 Preview: Named Constraints

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to…

• 6 min read
IntelliGen , Specman , debug , Functional Verification , e , AOP , IES-XL

DAC Best User Track: Visualizing Debugging Using Transaction Explorer in SoC System…

One of the great things about DAC is the opportunity to meet new people and find…

• 2 min read
DAC , System Design and Verification , Incisive , SoC , Marvel

Survey Results and Commentary on The XJTAG Girls at DAC 2009

In my last post, I recounted the disproportionate buzz received by the "XJTAG Girls…

• 7 min read
DAC , Functional Verification , OVM , XJTAG

More Details on Post Silicon Embedded Software Verification With ISX

Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in…

• 3 min read
AXI , eVC , System Design and Verification , OVM , SoC , ISX , ARM , ESL , FPGA

Slides From DAC Virtual Platform Workshop

As a follow-up to my report on the DAC Virtual Platform Workshop I would like to…

• less than a min read
DAC , virtual platform , System Design and Verification

A Quick Look Back at DAC

Well, I had good intentions of blogging from DAC , or at least summarizing my four…

• 1 min read
DAC , Verification methodology , Functional Verification , Open Verification Methodology , OVM

A Classification of ESL - High Level Synthesis Tools

These days, there is a lot of talk of what the next design methodology for Digital…

• 3 min read
RTL , System C , ESL , System Design and Verification

Full System vs Sub-system Virtual Prototyping

There is a strong movement in the industry to move to create Virtual Prototypes of…

• 2 min read
TLM , RTL , System Design and Verification , virtual prototype

Intel vs ARM - Did the Embedded Systems Conference India Shed Light on the Battle…

Being a Brit, Cricket is never very far from my thoughts especially when travelling…

• 2 min read
Intel , Low Power , System Design and Verification , embedded software , ARM

Post-DAC 2009 Survey on The XJTAG Girls

One non-technology item that received an extraordinary buzz at DAC 2009 were the…

• 1 min read
DAC , Functional Verification

1st Ever Virtual Platform Workshop Deemed a Success

Yesterday DAC hosted the first ever Virtual Platform Workshop , a full day dedicated…

• 2 min read
DAC 2009 , virtual platform , System Design and Verification

Finding the Opportunities in ESL

I came to DAC 2009 looking for the industry trends in ESL, because as we all know…

• 2 min read
DAC 2009 , virtual platform , System Design and Verification , ESL High Level Synthesis

Day 1 of DAC is a Wrap

Well, it was a half day at DAC for me as I suffered a 2 hour flight delay from Minneapolis…

• 3 min read
DAC , TLM 2.0 , System C , OSCiI , System Design and Verification

Customer Questions About TLM-driven Design and Verification

In the latest blog published by Ron Wilson there were two questions about our TLM…

• 1 min read
System Design and Verification , TLM 2.0 , System C , C-to-Silicon , high level synthesis

DAC 2009 News: Specman 9.2 Highlights + Beta Program Invitation

Specmaniacs, With the start of DAC 2009, Team Specman is excited to finally be able…

• 1 min read
DAC , IntelliGen , Specman , Functional Verification , simvision , OVM e , e , SystemC , IES-XL
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