Verification - Cadence Blogs - Cadence Community

Free Webinar Thursday 10/13 -- Automating Assertion Generation for Simulation, Formal…

Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology…

TeamVerify 5 Oct 2011 • 1 min read

NextOp , Joe Hupcey III , ABV , methodology , interview , Formal Analysis , BugScope , Incisive , webinar , DVcon , assertion synthesis , assertions , IEV , Yuan Lu , Formal verification , IFV , Assertion-based verification , IES-XL

17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction…

In their presentation at the recent SystemC Japan conference, Renesas Micro Systems…

Jack Erickson 4 Oct 2011 • 3 min read

time-to-market , High-Level Synthesis , verification turnaround , TLM , C-to-Silcon , ROI , System-Level Design , SystemC , C-to-Silicon Compiler , productivity

Amazon’s New Kindles: More Steps Toward the Paperback Computer

While I understand that a new Kindle Fire at $199 MRSP is significantly more than…

jvh3 28 Sep 2011 • 4 min read

Verification IP , RPP , SaaS , Joe Hupcey III , paperback computer , Cadence VIP portfolio , Kindle , system realization , VIP , EDA360 , EDA , VSP , Palladium XP , tablet , Hosted Design Solutions , Jim Hogan , Rapid Prototyping Platform , Amazon , Steve Leibson , cloud computing

Technical Tip on How to Use HDL Assertions in e

While assertion callbacks have existed in Specman/e for several years now, several…

teamspecman 28 Sep 2011 • 2 min read

IntelliGen , Specman , Incisive Enterprise Simulator , Incisive , e , SVA , e language , team specman , OOP , assertions , eRM , simulation , AOP , verification , Assertion-based verification

edaForum: Evolving Devices from “All in One” to “One for All”

This week I had the pleasure to attend and to present at the 11th annual edaForum…

fschirrmeister 26 Sep 2011 • 7 min read

PCB , IMC , Intel , virtual platforms , edaForum , virtual prototypes , IP integration , System Development Suite , EDA360 , embedded software , Shirrmeister , IC/package co-design , one for all , hardware/software co-development , Power Analysis , System Design & Verification , Frank Schirrmeister , all in one , Eul , power , debugging , System Design and Verification

Missing Real-World Assertions in Computer-Land

I was reviewing the page view statistics on the Cadence Functional verification…

tomacadence 26 Sep 2011 • 3 min read

uvm , ABV , outlook , Functional Verification , formal , assertions , Assertion-based verification

Virtual Platform UART Use Number 3: Using gdb to Debug a Software Application

This is the next installment in my series covering the uses of the venerable UART…

jasona 22 Sep 2011 • 7 min read

virtual prototoypes , virtual platforms , TLM , GDB , debug , UART , embedded software , software , SystemC , debugging , linux , System Design and Verification

ARM/Cadence Video: How ACE Coherency Adds Value and Verification Complexity

The number of licensees for ARM's Cortex-A15 CPU core is growing rapidly, particularly…

PeteHeller 19 Sep 2011 • 1 min read

Verification IP , ACE , Cortex-A15 , Functional Verification , video , VIP , interconnect monitor , ACE verification , cache coherency , coherency , ARM

Tech Tip: The “Show Me” Witness Trace Short-Cut for Design Bring-Up

In a prior Team Verify post, Application Engineer Bin Ju talked about several applications…

TeamVerify 19 Sep 2011 • 1 min read

show me , ABV , Functional Verification , Formal Analysis , formal , ADS , Chris Komar , witness trace , IEV , Assertion-Driven Simulation , simulation , Formal verification , IFV , Assertion-based verification

Rumors of SystemVerilog’s Death Have Been Greatly Exaggerated

Our friend and fellow blogger JL Gray recently published a post with the provocative…

tomacadence 15 Sep 2011 • 2 min read

SystemVerilog , uvm , uvm world , universal verification methodology , UCIS , Accellera , JL Gray

Everything New is Old … Everything Old is New

The title of this post is taken from a fairly obscure 1982 record album (yes, vinyl…

tomacadence 9 Sep 2011 • 2 min read

gate level , Functional Verification , LEC , RTL , DRC , LVS , EDA , old , gate-level , new , simulation

Virtual Platform UART Use Number 2: Using telnet to Connect to a UART

Welcome to the next installment in my series about different ways to use the venerable…

jasona 6 Sep 2011 • 4 min read

Virtual System Platform , TLM , virtual platform , UART , System Design and Verification , telnet , embedded software , xterm , virtual prototype , software , SystemC , linux , ESL

Can Your Verification Survive “Boot Camp”?

In Silicon Valley there is a popular fitness program called "Boot Camp" where people…

TeamVerify 24 Aug 2011 • 1 min read

ABV , boot camp , Functional Verification , Formal Analysis , formal , Incisive , assertions , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

What Does SystemC Mean for Design and Verification?

My colleague Jack Erickson recently published in the Cadence System Design and…

tomacadence 23 Aug 2011 • 3 min read

Virtual System Platform , TLM , uvm world , Functional Verification , Incisive Enterprise Simulator , VSP , C-to-Silicon , SystemC , IES-XL

If Only Carl Friedrich Gauss had IntelliGen in 1850

The N-queens issue is a challenging but standard puzzle when it comes to the world…

teamspecman 18 Aug 2011 • 5 min read

N-queens , IntelliGen , Specman , Object Oriented Programming , Functional Verification , Testbench simulation , e , OVM-e , team specman , specman elite , multi-language , Gauss , simulation , Rubik's Cube , AOP , Trailblazer

Virtual Platform UART Use Number 1: Connecting to an Interactive Terminal

Welcome to the first example of using a UART in a Virtual Platform. For those just…

jasona 18 Aug 2011 • 8 min read

Virtual System Platform , virtual platforms , Embecosm , virtual prototypes , UART , System Design and Verification , System Development Suite , xterm , SystemC

UCIS Coverage Standard -- Innovation Means Business

Open solutions are just curiosities until the ecosystem figures out how to turn…

Team MDV 17 Aug 2011 • 1 min read

metric-driven , coverage , Functional Verification , Metric Driven Verification , EDA360 , Incisive , Enterprise Manager , Plan and metrics management , UCIS , Accellera , coverage driven verification (CDV) , MDV

What I Learned Traveling Across the Silicon Prairie

Inspired by Brian Fuller's cross-country "Drive for Innovation" , last week I jumped…

jvh3 16 Aug 2011 • 1 min read

Silicon Prarie , Joe Hupcey III , ABV , Functional Verification , Formal Analysis , formal , ADS , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

Verifying AMBA® 4 ACE Designs – Cadence is Ready to Help, Now

ACE is here. Are you ready? Designers of multimedia smartphones, tablets, and other…

PeteHeller 15 Aug 2011 • 1 min read

Verification IP , ACE , Functional Verification , VIP , tablet , AMBA , Smartphone , EE Times

IP Cannot be an Efficient Abstraction Level Without SystemC!

EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction…

Jack Erickson 12 Aug 2011 • 3 min read

High-Level Synthesis , IP , TLM , RTL , abstraction , IP re-use , EDN , SoC , IP assembly , system design , SystemC , HLS , System Design and Verification

Virtual Flash Memory Gets Real

This week's Flash Memory summit will not only highlight the IP Cadence delivers,…

Steve Brown 8 Aug 2011 • 1 min read

Virtual System Platform , IP , Memory , virtual platforms , TLM , virtual prototypes , TLM 2.0 , flash memory , Incisive Software Extensions , ISX , Flash Memory Summit , System Design and Verification

A Must Read: the ARM Cortex-A Programmer's Guide

For the last couple of years, I have been getting a lot of e-mail from different…

jasona 4 Aug 2011 • 2 min read

ARM Cortex-A , virtual platforms , programmer's guide , virtual prototypes , Cortex-A , virual platform , ARM Architecture , ARM , linux , System Design and Verification

The Return of the Son of Real-World Assertions

I've received some nice feedback on my previous two posts about real-world situations…

tomacadence 1 Aug 2011 • 3 min read

ABV , Functional Verification , formal , assertions , Assertion-based verification

Four Uses for the Venerable Virtual Platform UART

The Universal Asynchronous Receiver/Transmitter (UART) is one of the oldest hardware…

jasona 27 Jul 2011 • 2 min read

Some Reflections on the Development of UVM World

In a recent blog post , I celebrated our donation of the Cadence-developed UVM…

tomacadence 22 Jul 2011 • 3 min read

uvmworld.org , uvm , uvm world , Functional Verification , OVM , universal verification methodology , Accellera , verification

ARM Generic Interrupt Controller HOWTO

Way back in 2004, I wrote a book called Co-Verification of Hardware and Software…

jasona 22 Jul 2011 • 5 min read

Virtual System Platform , Cortex-A9 , System Design and Verification , Cortex-A , howto , ARM Generic Interrupt Controller , SystemC , GIC , ARM , Wadikar , Generic Interrupt Controller

Video: Discussion with EET’s Brian Fuller on EDA, Engineers, and Social Media

At DAC I had the honor of being interviewed by EE Times editor Brian Fuller on my…

jvh3 21 Jul 2011 • 1 min read

Brian Fuller , DAC , Joe Hupcey III , tweeting , videos , interview , Blogging , YouTube , blogs , Facebook , OrCAD , CtoSilicon , Twitter , Social Media , EE Times , DAC360

Enterprise Planner - CSV Import Tech Tip

Are you interested in an automating your directed or random test list that you manually…

Team MDV 15 Jul 2011 • 1 min read

metric-driven , Functional Verification , Metric Driven Verification , CSV , vPlan , tech tips , EDA360 , Incisive , Enterprise Manager , Enterprise Planner , MDV , Excel , verification

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