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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Video: DVCon 2011 Update From NextOp CEO Yunshan Zhu

At DVCon 2011 I had the opportunity to catch-up with NextOp's CEO Yunshan Zhu, where…

• less than a min read
Cadence Connections , NextOp , uvm , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Zhu , Palladium XP , SVA , DVcon , assertion synthesis , MDV , IEV , Formal verification , IFV , IES-XL

Save The Date: Free Webinar on Automated SoC Connectivity Verification This Thursday…

We interrupt our technically oriented blogging to shamelessly promote a free webinar…

• 1 min read
ABV , methodology , Functional Verification , formal , SoC Connectivity , IEV , Formal verification , IFV

A Modest Proposal: Using Formal to Close Coverage Gaps

In my last blog post , I summarized some of our activities at DVCon and mentioned…

• 4 min read
NextOp , coverage , Functional Verification , Formal Analysis , formal , BugScope , Breker , DVcon , assertion synthesis , assertions , Closure , metrics , CVC , Formal verification

DATE Spotlights System Development University Investment in Europe

In this guest blog Markus Winterholer, R&D engineer at Cadence, explains why he's…

• 2 min read
university , DATE , Winterholer , UML , Daedalus , University Booth , VOCIS , System Design and Verification

Video: Optimizing Area and Power Using Formal Methods

At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel…

• 1 min read
Low Power , ABV , methodology , Formal Analysis , formal , Freescale , Incisive , Chris Komar , DVcon , IFV

Video: New Cadence Verification IP Catalog (With Denali Inside!)

Clearly UVM 1.0 was the main story at DVCon last week, but there was other big news…

• less than a min read
uvm , Functional Verification , ABVIP , Cadence VIP portfolio , OVM , VIP , EDA360 , Verification IP modeling , DVcon , eRM

TLM 2.0, UVM 1.0 and Functional Verification

The DVCon 2011 conference was held this week and the Accellera Universal Verification…

• 8 min read
SystemVerilog , uvm , TLM , Functional Verification , OVM , TLM 2.0 , ports , DVcon , Accellera , SystemC , Accellera VIP TSC , VMM , verification

DVCon? Are You Sure It's Not UVMCon or MSVCon?

As I write this, I've just returned from the most important conference and tradeshow…

• 2 min read
uvm , Functional Verification , MSV , EDA360 , Mixed-Signal , random test , DVcon , Accellera , mixed signal , verification

Specman Application Note: Improving Verification Productivity With Dynamic Load and…

Are you looking for new approaches to improve your verification productivity by 40…

• 3 min read
IntelliGen , Specman , metric driven verification (MDV) , Functional Verification , vPlan , simvision , EDA , Incisive , e language , team specman , specman elite , Aspect Oriented Programming , testbench , Incisive Enterprise Simulator (IES) , AOP , IES-XL

Do You Have a DATE with Software? Cadence Does!

How important is the software market to Cadence and as an element of the EDA360 vision…

• 3 min read
DATE , IP , IP-XACT , debug , RTL , System Design and Verification , SoC , virtual prototype , software , Virtual Platforms

At DVCon 2011 Next Week

Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you…

• 2 min read
Industry Insights , ABV , TLM , Functional Verification , formal , OSCI , OVM , EDA360 , Coverage-Driven Verification , EDA , Mixed Signal Verification , Incisive , Mixed-Signal , DVcon , OOP , multi-language , SystemC , Formal verification , techtorial , AOP

Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

Don't lose touch with what's new in the world of SystemC! Cadence is a long time…

• 2 min read
virtual platforms , virtual prototypes , System Design and Verification , OSCI , DVcon , Accellera , Jim Hogan , IEEE P1666 , SystemC , NASCUG , SystemC Day

Celebrating the UVM 1.0 Release, or the Gadfly Eats a Little Crow

As I hope you have all seen by now, Accellera has announced the official production…

• 2 min read
uvm , methodology , Functional Verification , VIP , VIP-TSC , Register Package , Accellera , gadfly , verification

The Increasing Role of SystemC in System Design

Today's post is less technical and a bit more theoretical, but I promise that my…

• 4 min read
debug , C , system design , SystemC , Virtual Platforms , Synthesis , Modeling , C++ , debugging , simulation , System Design and Verification

Formal Driven MDV – A New Tool for your Toolbox

Have you considered adding formal to your metric driven verification flow? Maybe…

• 2 min read
metric-driven , coverage , Functional Verification , Metric Driven Verification , Formal Analysis , formal , Incisive , MDV , simulation , Formal verification

Being a Part of Something Truly Remarkable - UVM

For just over two years I have had the honor of playing a role in a dramatic example…

• 2 min read
uvm , Functional Verification , EDA360 , Incisive , Accellera VIP TSC , synopsys , IES , Mentor

The Tale of the Silicon Re-Spin and the Bug That Got Away

I'd like to continue my blog series discussing corner-case conditions of various…

• 4 min read
conformal , corner cases , clock domain crossings , CDC , bug , FIFO

The Role of Coverage in Formal Verification, Part 3

.special { font-family: 'Courier New' !important; } In the last post of this…

• 5 min read
ABV , methodology , verification strategy , coverage , metric driven verification (MDV) , Functional Verification , Formal Analysis , Model-checking , formal , Coverage-Driven Verification , Incisive , SVA , PSL , metric-driven verification , coverage driven verification (CDV) , assertions , IEV , simulation , IFV

Why the Demand for Acceleration and Emulation is Growing

The dream of any marketer is a growing demand for its product line. Let me start…

• 3 min read
emulator , ASIC , Acceleration , virtual platform , System Design and Verification , OVM , Palladium , Low power verification and analysis , Emulation , virtual prototype , System Design & Verification , Hardware/software co-verification , simulation , verification

De-Mystifying SystemC: What is TLM?

In my last post I briefly mentioned that when designing hardware with SystemC, you…

• 2 min read
High-Level Synthesis , Registers , TLM , Models , C to Silicon , transaction level modeling , SystemC , Modeling , System Design and Verification

What Could Be Simpler than a Request-Acknowledge Handshake?

My last few blog posts have included three corner-case conditions that led to bugs…

• 3 min read
Functional Verification , bugs , corner cases , formal , intent , assertions , simulation

The Role of Coverage in Formal Verification, Part 2 Continued…

Recall that three main questions need to be answered to attain coverage in formal…

• 3 min read
ABV , methodology , verification strategy , coverage , debug , Functional Verification , Formal Analysis , formal , Coverage-Driven Verification , CDV , Incisive , SVA , PSL , metric-driven verification , assertions , IEV , Incisive Enterprise Simulator (IES) , IFV

SystemC: It's Neither Complicated Nor Belligerent!

I was recently talking to a customer who was looking to move up in abstraction from…

• 2 min read
High-Level Synthesis , TLM , C to Silicon , system , SystemC , C++ , ESL , System Design and Verification

Video: Distinguished Engineer Alok Jain on Formal and Assertion-Based Verification…

Kicking off 2011, my colleague Alok Jain -- a Distinguished Engineer at Cadence who…

• less than a min read
Alok Jain , IP , ABV , verification strategy , metric driven verification (MDV) , Functional Verification , Formal Analysis , ABVIP , formal , EDA360 , Coverage-Driven Verification , CDV , assertions , MDV , IEV , Incisive Enterprise Simulator (IES) , IFV , verification

The Role of Coverage in Formal Verification, Part 2

As noted in the prior installment of this series, there are three main questions…

• 4 min read
ABV , methodology , verification strategy , coverage , Functional Verification , Formal Analysis , Model-checking , formal , Coverage-Driven Verification , Incisive , SVA , PSL , assertions , IEV , IFV , verification

Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog

A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and…

• 3 min read
SystemVerilog , Specman , OVM ML , Testbench simulation , OVM e , EDA , e , e language , team specman , Aspect Oriented Programming , eRM , simulation , AOP , Functional Verificatioa , IES-XL

Achieve the Next Level of Verification Productivity with Specman Advanced Option

Advanced verification customers are seeing their verification environments getting…

• 3 min read
Specman , Object Oriented Programming , debug , Functional Verification , Testbench simulation , e , e language , team specman , Aspect Oriented Programming , eRM , testbench , IES , AOP , verification , IES-XL , Trailblazer

In Verification, Failing to Plan = Planning to Fail

So I know you tell your kids this, you tell your spouse this, you heard it from…

• 2 min read
uvm , Verification methodology , metric driven verification (MDV) , Functional Verification , vPlan , MDV techtorial , verification planning , Incisive , Enterprise Manager , Enterprise Planner , FPGA , verification
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