Featured

Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Creating SystemC TLM-2.0 Peripheral Models

Over two years ago, I made some experiments and raised some requirements for an effective…

• 8 min read
Virtual System Platform , virtual platforms , TLM , IP-XACT , Models , virtual prototypes , System Design and Verification , TLM 2.0 , embedded software , VSP , TLM-2.0 , Team ESL , peripheral , SystemC , ESL

More Examples of Missing Real-World Assertions

Back in May, I published a blog post with examples of real-world situations that…

• 3 min read
ABV , asssertion-based verification , Functional Verification , formal , assertions

Celebrating the Success of the UVM World Web Site

In case you missed it, Cadence issued a press release last week announcing that we…

• 2 min read
uvm , uvm world , universal verification methodology , Accellera

True Stories of Assertion Driven Simulation (ADS) in the Wild

Ever since Assertion-Driven Simulation (ADS) became available, I have been working…

• 4 min read
AXI , ABV , Verification methodology , Functional Verification , Formal Analysis , ABVIP , formal , simvision , VIP , ADS , DDR , Club Formal , Constraints , IEV , Assertion-Driven Simulation , Formal verification , Assertion-based verification

Video: Distinguished Engineer Mike Stellfox on UVM, the Debug Bottleneck, and System…

My colleague and Cadence Distinguished Engineer Mike Stellfox leads a group of trailblazers…

• less than a min read
DAC , uvm , debug , system realization , Mike Stellfox , Accellera , SystemC , Trailblazer

Before DAC, There Was Club Formal – An Event Series Completely Focused on Formal…

To complement our support of DAC, CDNLive, and other large-scale events, where the…

• 1 min read
events , ABV , verification strategy , Functional Verification , Formal Analysis , formal , Incisive , Incisive Seminar , ADS , Oski Technology , Silicon Realization , assertions , Club Formal , ClubT , IEV , Assertion-Driven Simulation , Formal verification , IFV , verification , Assertion-based verification

Full Sequence Coverage in a Single Line of e Code?

I was asked recently about how to easily collect coverage on the sequences generated…

• 1 min read
Specman , e , OVM-e , e language , team specman , specman elite , AOP

Video: Duolog at DAC 2011 Update – Automating Design and Verification IP Integra…

One of the key tenants of the EDA360 vision is the need for scalable, correct-by…

• 1 min read
Cadence Connections , DAC , uvm , Virtual System Platform , IP , videos , IP-XACT , TLM 2.0 , VIP , EDA360 , Duolog , Incisive , Socrates , AMBA , ARM , David Murray

Video: DAC 2011 Update From NextOp CEO Yunshan Zhu

At DAC 2011 I had the opportunity to reconnect with Yunshan Zhu, the CEO of NextOp…

• less than a min read
Cadence Connections , NextOp , DAC , uvm , ABV , Yunshan Zhu , verification strategy , Functional Verification , Formal Analysis , BugScope , assertion synthesis , assertions , Design Automation Conference , Formal verification , verification , Assertion-based verification

Planes, Trains and Automobiles: European Seminar Series

A couple of blog posts ago, I talked about the worldwide functional verification…

• 3 min read
Functional Verification , Europe , formal , Incisive , Mixed-Signal , EMEA , metric-driven verification , MDV , IEV , IFV

Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open…

Specmaniacs and IES-XL users around the world know that Integrated Development Environment…

• less than a min read
DAC , eclipse , uvm , Specman , Functional Verification , Amitroaie , OVM , e , DVT , e language , AMIQ , eRM , IDE , verification , IES-XL

Video: Formal Verification Service Provider Oski Technology at DAC 2011

At DAC 2011, both myself and fellow Team Verify member Tom Anderson felt a distinct…

• 1 min read
DAC , ABV , verification strategy , Verification methodology , Functional Verification , Formal Analysis , formal , Oski Technology , assertions , Formal verification , verification , Assertion-based verification

Photo Essay and Comments on DAC 2011 in San Diego, CA

In addition to the annotated image gallery ( click here or on the image), below are…

• 2 min read
DAC , Joe Hupcey III , ABV , asssertion-based verification , Formal Analysis , formal , EDA360 , EDA , ADS , Oski Technology , Assertion-Driven Simulation , Formal verification , cloud computing

Is e Old? Yes. Is it Outdated? Definitely Not!

I was at the Design Automation Conference (DAC) last week showcasing our latest,…

• 2 min read
IEEE 1647 , DAC , Object Oriented Programming , Corey Goss , EDA , e , team specman , Aspect Oriented Programming , eRM , AOP

Looking Back at DAC

Last week was the 48 th Design Automation Conference (DAC), held in lovely San…

• 3 min read
DAC , uvm , Functional Verification , Formal Analysis , Denali Party , San Diego , Design Automation Conference

A SystemC Virtual Platform Overflowing the Stack -- Just Before DAC

Thanks to all who stopped by the Cadence booth to see and talk about the Cadence…

• 6 min read
DAC , Virtual System Platform , virtual platforms , virtual prototypes , Demo , stack overflow , SystemC , System Design and Verification

Using the ARM Profiler with the Cadence Virtual System Platform

I have posted a new article over at blogs.arm.com covering the current integration…

• less than a min read
Virtual System Platform , virtual platforms , ARM Profiler , virtual prototypes , proflling , software , System Design & Verification , ARM

Image Gallery: Cadence-Denali Party at DAC 2011 in San Diego

The 20nm roadmap . TSMC reference flow 12 . The UVM 1.1 release . Verification IP…

• 1 min read
gallery , DAC , uvm , ACE , Joe Hupcey III , ABV , images , Functional Verification , Cadence VIP portfolio , formal , VIP , 20nm , EDA360 , TSMC , Denali Party , EDA , ADS , Denali , party , assertions , ARM , Assertion-Driven Simulation , Formal verification , Assertion-based verification

DAC Cheesy Must See List: Enterprise Manager

Understandably, EDA industry observer John Cooley had to edit down all the submissions…

• 1 min read
Functional Verification , Metric Driven Verification , Enterprise Manager , MDV

DAC Preview: The Complete Incisive Enterprise Verifier Submission to John Cooley…

Understandably, EDA industry observer John Cooley had to edit down all the submissions…

• 1 min read
DAC , Joe Hupcey III , ABV , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , EDA , Incisive , ADS , Tom Anderson , SVA , Chris Komar , PSL , assertions , gadfly , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

DAC Preview: Make Assertions Come Alive with Assertion-Driven Simulation

While Assertion-Based Verification (ABV) has been around for many years, ABV has…

• 2 min read
DAC , Joe Hupcey III , ABV , Functional Verification , Formal Analysis , formal , ADS , Tom Anderson , SVA , Chris Komar , PSL , assertions , IEV , Assertion-Driven Simulation , Formal verification , Assertion-based verification

OVM 2.1.2 -- Getting You Ready for UVM

Talk about stability -- OVM 2.1.1 has had 18 months as the core of Accellera's UVM…

• 1 min read
SystemVerilog , DAC , uvm , OVM , Incisive , OVM SV , Funcional Verification , Accellera VIP TSC , IES , OVMWorld , OVM 2.1

Pre-RTL Software Development -- You Can't Get Your Product to Market Without It!

It's been an exciting month for the System Realization team with the announcement…

• 2 min read
Virtual System Platform , TLM 2.0 , virtual prototype

Blazing a Trail With Ubuntu

One of the most popular blogs I wrote is running Incisive on Ubuntu . I have had…

• 3 min read
SystemC debugging , Virtual System Platform , debug , Ubuntu , SystemC , debugging , linux , System Design and Verification

A Look at the Ongoing Functional Verification Seminar Series

Being a Marketing guy, one thing that I really enjoy is getting on the road for…

• 2 min read
Functional Verification , formal , Incisive , Mixed-Signal , metric-driven verification , MDV , IEV , IFV

Panel Discussion: Applying High-Level Synthesis in an SoC Flow

Last Thursday, EETimes hosted a virtual System on Chip event focused on IP integration…

• 6 min read
IP , system on chip , BDTI , SoC , EETimes , Tensilica , Bluespec , SystemC , Synthesis , high level synthesis , HLS , C++ , ESL , System Design and Verification

Sometimes the Real World Needs Assertions Too

Every once in a while, I like to do a lightweight blog post linking my work world…

• 3 min read
ABV , asssertion-based verification , Functional Verification , formal , assertions

2011 CDNLive EMEA Highlights and Image Gallery: An EDA360 Spring Festival of Del…

Last week teammate Adam Sherer and I had the honor of representing the Incisive functional…

• 3 min read
RPP , Joe Hupcey III , Specman , Virtual System Platform , AVS , CDNLive , Functional Verification , Adaptive Voltage Scaling , Palladium , System Development Suite , EDA360 , VSP , Incisive , festival , Adam Sherer , Palladium XP , Philippe Magarshack , EMEA , Rapid Prototyping Platform , IEV , Incisive Enterprise Simulator (IES) , IES , Techcon , stmicroelectronics , IES-XL
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