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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

UVM - The Progress Continues With Reference Flow

As 2010 ends and 2011 begins, the most important thing that came out of the Universal…

• 1 min read
uvm , Functional Verification , EDA360 , Coverage-Driven Verification , EDA , AMIQ , verification

A Look Back at ARM Techcon 2010: Surprising Keynotes, New Products, and Lego!

The acid test of any conference is how long after the keynotes, panels, and demos…

• 4 min read
A-15 , Industry Insights , Cortex , GPU , IBM , Mali , EDA360 , linaro , blogs , ecosystem , moore's law , EUV litho , Marvell , ARM , Techcon

System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part 1)

2010 was a very dynamic year for the electronic systems industry overall, and for…

• 5 min read
High-Level Synthesis , TLM2 , ASIC , TLM-driven design , CDNLive , cadence , Acceleration , C to Silicon , system realization , System Design and Verification , C-to-Silcon , EDA360 , ASIC/ASSP , rtl compiler , Co-verification , metric-driven verification , C-to-Silicon Compiler , Virtual Platforms , Synthesis , high level synthesis , ARM , MDV , ESL , System Design and Verification

Those Corner-Case Conditions Caught You Again!

In my last blog post , I related a story from my engineering past in which I learned…

• 3 min read
sjc , Functional Verification , bugs , corner cases , airport

How Do You Debug Your Testbench when it Won’t Stand Still?

The task of debugging a simulation problem in your design can be a difficult and…

• 1 min read
whitepaper , uvm , debug , Functional Verification , bugs , simvision , OVM , Incisive , testbench

On-Demand Webinar: TLM Design and High-Level Synthesis

In case you missed it last week, Mark Warren delivered a very informative webinar…

• less than a min read
TLM , C to Silicon , webinars , RTL , System C , SystemC , System Design and Verification

Corner-Case Conditions Will Get You Every Time

Experienced verification engineers know that most killer bugs lurk deep in the corners…

• 2 min read
Functional Verification , bugs , corner cases , dec , Gordon Bell

New Interview with Partner Zocalo on Their Assertion Creation Philosophy and Approach…

Heads-up Team Verify subscribers: on his "Industry Insights" blog Richard Goering…

• less than a min read
DAC , ABV , Zocalo , verification strategy , Verification methodology , Functional Verification , formal , assertions , verification

A SystemC TLM 2.0 ARM Linux Boot Loader

Earlier this year I wrote an article with some details related to loading Linux into…

• 6 min read
TLM2 , virtual platforms , System Design and Verification , TLM 2.0 , embedded software , boot loader , software , SystemC , ARM , linux , System Design and Verification , kernel

“Everything Assertion Based” -- Assertion-Based Verification (ABV) Comes of Age for…

Preface: are you having trouble (re-)igniting interest in formal, muti-engine, and…

• 5 min read
NextOp , ABV , Zocalo , Functional Verification , Formal Analysis , formal , VIP , PSL , assertion synthesis , metric-driven verification , coverage driven verification (CDV) , assertions , AMBA , MDV , IEV , IFV

Evolution and Synthesis

If you have not yet seen it, Jim Hogan and Paul McLellan wrote a great piece over…

• 2 min read
High-Level Synthesis , RTL , Hogan , EETimes , SystemC , evolution , HLS , McLellan

Does It Get Any Better than CDNLive! India?

I've just returned from CDNLive! India in Bangalore, fired up with the huge crowd…

• 3 min read
CDNLive , formal , OVM , ISX , MDV , IFV , techtorial , India , verification

“Formal Design” or “Formal Verification”-- What is the Right Label?

Shortly after DAC 2010, Gabe Morretti wrote a couple of interesting blogs (reference…

• 3 min read
DAC , uvm , ABV , CDNLive , Functional Verification , formal , OVM , EDA360 , EDA , SoC , Silicon Realization , SoC Connectivity , connectivity , IFV

Broadcom Presentation Shows Value of Transaction-Based Acceleration

Wow - what a paper! At CDNLive! Silicon Valley 2010 , the joint paper from Broadcom…

• 1 min read
CDNLive , Acceleration , System Design and Verification , Palladium , broadcom , Emulation , transaction-based , simulation , verification

Open Mobile Summit -- What‘s Happening in the World of Applications

I attended last week's Open Mobile Summit in San Francisco last week. This is a twice…

• 4 min read
Open Mobile Summit , applications , android , EDA360 , google , apps , superphones , smartphones

System Bring-Up - THE Critical Path in the System Development Process

The electronic industry is moving from hardware-defined products to software-defined…

• 2 min read
prototyping , Bring-up , Acceleration , debug , system realization , Palladium , Emulation , bringup , System Design and Verification , verification

2010 CDNLive Silicon Valley Photo Blog: Silicon Realization, ABV, OVM, MDV, Specman…

If you are running short on time and can't view all the videos of the 2010 CDNLive…

• less than a min read
SystemVerilog , Cadence Connections , NextOp , AMS , uvm , Specman , ABV , Zocalo , verification strategy , CDNLive , Functional Verification , Formal Analysis , formal , OVM , EDA360 , Mixed Signal Verification , e , SoC , SVA , ISX (Incisive Software Extensions) , Silicon Realization , AMIQ , assertion synthesis , Aspect Oriented Programming , ISX , MDV , IEV , IFV , AOP

The Amazing Diversity of the SoC Conference

Although I attend a number of conferences and tradeshows each year, most of these…

• 3 min read
SOC Conference , uvm , Multi-Core , SoC , multicore , yield , verification

Using Scoreboards and Virtual Platforms for Software Verification

Today I'm running a guest article written by Henry Von Bank of Posedge Software …

• 4 min read
scoreboards , software verification , virtual platforms , posedge , virtual prototypes , Incisive , ISX , System Verification , linux

Verification Goldmine: 50 User Papers on Formal, Multi-Engine, and Assertion-Based…

With all due respect to our Tech Pubs writers, Solutions Architects, and contributors…

• 8 min read
verifier , DAC , ABV , methodology , CDNLive , metric driven verification (MDV) , debug , Functional Verification , Formal Analysis , formal , Incisive , SVA , Silicon Realization , PSL , DVcon , AMBA , MDV , IEV , IFV

CDNLive! Silicon Valley 2010 in the Rear-View Mirror

Well, we all survived another very busy CDNLive! event last week. Since I posted…

• 2 min read
uvm , CDNLive , OVM , EDA360 , MDV , techtorial , verification

User Views -- Migrating From FPGA-Based Prototyping to Palladium

In recent posting published by John Cooley on Deepchip.com, users compared FPGA-based…

• 1 min read
emulator , deepchip , prototyping , Palladium , Emulation , Cooley , FPGA

The Increasingly Hazardous World of FPGA Verification

Last week saw the publication of two interesting blog posts regarding the growing…

• 3 min read
uvm , Verification methodology , Functional Verification , Formal Analysis , OVM , FPGA

CDNLive! -- Israel and the U.S.

The Cadence Design Network provides a great way to learn about the latest design…

• 1 min read
CDNLive , system realization , Emulation , software , Israel , CDNLive! , embedded , System Design and Verification

Android, Linaro, and 10 Other Useful Embedded Linux Links

The state of Minnesota is unofficially divided into two parts; The Cities and The…

• 1 min read
android , System Design and Verification , linaro , software , linux , Embedded Linux , embedded

e Templates and e Macros -- An Update for Specman Users

A couple of recent blogs have mentioned the feature of e templates, which was added…

• 2 min read
Specman , Functional Verification , Incisive , e , team specman , macros , AOP , IES-XL

Team Verify at CDNLive Silicon Valley Next Week – ABV, Formal, Multi-Engine Verification…

At next week's CDNLive! Silicon Valley in San Jose, California, Cadence will cover…

• 1 min read
NextOp , IP , ABV , methodology , Zocalo , CDNLive , Functional Verification , Formal Analysis , formal , EDA360 , Incisive , Silicon Realization , assertion synthesis , IEV , IFV

A Preview of Verification Sessions at CDNLive! Silicon Valley

As Cadence followers well know, our annual worldwide series of CDNLive! events is…

• 2 min read
uvm , ABV , CDNLive , OVM , MDV , techtorial , verification
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