Verification - Cadence Blogs - Cadence Community

Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

Don't lose touch with what's new in the world of SystemC! Cadence is a long time…

Steve Brown 24 Feb 2011 • 2 min read

virtual platforms , virtual prototypes , System Design and Verification , OSCI , DVcon , Accellera , Jim Hogan , IEEE P1666 , SystemC , NASCUG , SystemC Day

Celebrating the UVM 1.0 Release, or the Gadfly Eats a Little Crow

As I hope you have all seen by now, Accellera has announced the official production…

tomacadence 22 Feb 2011 • 2 min read

uvm , methodology , Functional Verification , VIP , VIP-TSC , Register Package , Accellera , gadfly , verification

The Increasing Role of SystemC in System Design

Today's post is less technical and a bit more theoretical, but I promise that my…

jasona 22 Feb 2011 • 4 min read

debug , C , system design , SystemC , Virtual Platforms , Synthesis , Modeling , C++ , debugging , simulation , System Design and Verification

Formal Driven MDV – A New Tool for your Toolbox

Have you considered adding formal to your metric driven verification flow? Maybe…

Team MDV 21 Feb 2011 • 2 min read

metric-driven , coverage , Functional Verification , Metric Driven Verification , Formal Analysis , formal , Incisive , MDV , simulation , Formal verification

Being a Part of Something Truly Remarkable - UVM

For just over two years I have had the honor of playing a role in a dramatic example…

Adam Sherer 18 Feb 2011 • 2 min read

uvm , Functional Verification , EDA360 , Incisive , Accellera VIP TSC , synopsys , IES , Mentor

The Tale of the Silicon Re-Spin and the Bug That Got Away

I'd like to continue my blog series discussing corner-case conditions of various…

tomacadence 17 Feb 2011 • 4 min read

conformal , corner cases , clock domain crossings , CDC , bug , FIFO

The Role of Coverage in Formal Verification, Part 3

.special { font-family: 'Courier New' !important; } In the last post of this…

TeamVerify 14 Feb 2011 • 5 min read

ABV , methodology , verification strategy , coverage , metric driven verification (MDV) , Functional Verification , Formal Analysis , Model-checking , formal , Coverage-Driven Verification , Incisive , SVA , PSL , metric-driven verification , coverage driven verification (CDV) , assertions , IEV , simulation , IFV

Why the Demand for Acceleration and Emulation is Growing

The dream of any marketer is a growing demand for its product line. Let me start…

Ran Avinun 14 Feb 2011 • 3 min read

emulator , ASIC , Acceleration , virtual platform , System Design and Verification , OVM , Palladium , Low power verification and analysis , Emulation , virtual prototype , System Design & Verification , Hardware/software co-verification , simulation , verification

De-Mystifying SystemC: What is TLM?

In my last post I briefly mentioned that when designing hardware with SystemC, you…

Jack Erickson 3 Feb 2011 • 2 min read

High-Level Synthesis , Registers , TLM , Models , C to Silicon , transaction level modeling , SystemC , Modeling , System Design and Verification

What Could Be Simpler than a Request-Acknowledge Handshake?

My last few blog posts have included three corner-case conditions that led to bugs…

tomacadence 31 Jan 2011 • 3 min read

Functional Verification , bugs , corner cases , formal , intent , assertions , simulation

The Role of Coverage in Formal Verification, Part 2 Continued…

Recall that three main questions need to be answered to attain coverage in formal…

TeamVerify 27 Jan 2011 • 3 min read

ABV , methodology , verification strategy , coverage , debug , Functional Verification , Formal Analysis , formal , Coverage-Driven Verification , CDV , Incisive , SVA , PSL , metric-driven verification , assertions , IEV , Incisive Enterprise Simulator (IES) , IFV

SystemC: It's Neither Complicated Nor Belligerent!

I was recently talking to a customer who was looking to move up in abstraction from…

Jack Erickson 24 Jan 2011 • 2 min read

High-Level Synthesis , TLM , C to Silicon , system , SystemC , C++ , ESL , System Design and Verification

Video: Distinguished Engineer Alok Jain on Formal and Assertion-Based Verification…

Kicking off 2011, my colleague Alok Jain -- a Distinguished Engineer at Cadence who…

jvh3 23 Jan 2011 • less than a min read

Alok Jain , IP , ABV , verification strategy , metric driven verification (MDV) , Functional Verification , Formal Analysis , ABVIP , formal , EDA360 , Coverage-Driven Verification , CDV , assertions , MDV , IEV , Incisive Enterprise Simulator (IES) , IFV , verification

The Role of Coverage in Formal Verification, Part 2

As noted in the prior installment of this series, there are three main questions…

TeamVerify 20 Jan 2011 • 4 min read

ABV , methodology , verification strategy , coverage , Functional Verification , Formal Analysis , Model-checking , formal , Coverage-Driven Verification , Incisive , SVA , PSL , assertions , IEV , IFV , verification

Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog

A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and…

teamspecman 18 Jan 2011 • 3 min read

SystemVerilog , Specman , OVM ML , Testbench simulation , OVM e , EDA , e , e language , team specman , Aspect Oriented Programming , eRM , simulation , AOP , Functional Verificatioa , IES-XL

Achieve the Next Level of Verification Productivity with Specman Advanced Option

Advanced verification customers are seeing their verification environments getting…

teamspecman 18 Jan 2011 • 3 min read

Specman , Object Oriented Programming , debug , Functional Verification , Testbench simulation , e , e language , team specman , Aspect Oriented Programming , eRM , testbench , IES , AOP , verification , IES-XL , Trailblazer

In Verification, Failing to Plan = Planning to Fail

So I know you tell your kids this, you tell your spouse this, you heard it from…

Team MDV 13 Jan 2011 • 2 min read

uvm , Verification methodology , metric driven verification (MDV) , Functional Verification , vPlan , MDV techtorial , verification planning , Incisive , Enterprise Manager , Enterprise Planner , FPGA , verification

Applying Digital-Centric Verification Methodologies to Analog

A majority (if not all) SoCs today are mixed signal. Increasingly, the analog and…

teamspecman 12 Jan 2011 • 4 min read

AMS , Low Power , Real Value Modeling , Functional Verification , Mixed Signal Verification , Mixed-Signal , metric-driven verification , SoC Connectivity , System Verification , Incisive Enterprise Simulator (IES) , IP modeling , RVM

There's Another Simulation Failure! New SimVision Features Can Help

Simulation failures are seen quite often in design verification. Fortunately, with…

archive 12 Jan 2011 • 4 min read

uvm , debug , Functional Verification , simvision , Incisive , Silicon Realization

My Reason For Choosing e – a Much More Advanced Verification Language. What’s Your…

I'd like to share with you a story from many, many, many moons ago when I first evaluated…

teamspecman 12 Jan 2011 • 7 min read

SystemVerilog , Specman , debug , Functional Verification , e , e language , Aspect Oriented Programming , AOP

More on the Benefits of Metric-Driven Formal Analysis and Verification (MDV + ABV…

We interrupt R&D's Vinaya Singh's excellent series on "The Role of Coverage in Formal…

TeamVerify 11 Jan 2011 • 2 min read

Alok Jain , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , vPlan , corner cases , formal , EDA360 , verification planning , Coverage-Driven Verification , Enterprise Manager , intent , Enterprise Planner , Silicon Realization , coverage driven verification (CDV) , MDV , IEV , IFV , Coverage Driven Verification , verification

What Does Silicon Realization Mean for Verification Engineers?

Last May , I posed a question about what EDA360 means for verification engineers…

tomacadence 11 Jan 2011 • 2 min read

performance , uvm , Functional Verification , vPlan , formal , OVM , VIP , EDA360 , Multi-Core , Incisive , Silicon Realization , metric-driven verification , multicore , IEV , simulation , IES , IFV

How Elastic is Your Business?

Facing a verification overrun, you poached resources, clocked overtime, and kept…

Adam Sherer 10 Jan 2011 • 3 min read

Functional Verification , verification planning , profitability , business , elastic , metric-driven verification , MDV

Infinite Playbook for the Verification Superbowl

Its 4th and long, you're down by six, the clock is running out, and you are wary…

Team genIES 10 Jan 2011 • 2 min read

SystemVerilog , uvm , debug , Functional Verification , OVM , EDA360 , Multi-Core , Incisive , Silicon Realization , Incisive Enterprise Simulator (IES) , Accellera VIP TSC , simulation , IES

System Realization Webinars in 2010 -- A Summary

Last year was unprecedented for Cadence. We came up with the EDA360 vision , reorganized…

MayankBhatia 7 Jan 2011 • 5 min read

High-Level Synthesis , TLM , Fast Models , IP-XACT , Models , system realization , TLM 2.0 , Calypto , TSMC , Magillem , virual platform , virtual protoype , virtual prototype , Jeda , Imperas , Virtual Platforms , CircuitSutra , TLM 2.0-driven design , XtremeEDA , SystemC TLM2 , ESL , CoFluent , System Design and Verification

How I Nearly Had My Own “Subtract Bug” in a CPU Design

In a recent blog post , I talked about learning a public lesson on the importance…

tomacadence 4 Jan 2011 • 3 min read

divide , subtract bug , debug , Functional Verification , bugs , corner cases , Cydrome , subtract , add , verification

The Role of Coverage in Formal Verification, Part 1 of 3

As outlined in a prior post , new advances in formal and multi-engine technology…

TeamVerify 3 Jan 2011 • 4 min read

ABV , methodology , verification strategy , metric driven verification (MDV) , Functional Verification , Formal Analysis , ABVIP , Cadence VIP portfolio , formal , VIP , CDV , SVA , PSL , coverage driven verification (CDV) , assertions , MDV , IEV , IFV

More on the SystemC ARM Linux Boot Loader

My last post described a Linux Loader for ARM Virtual Platforms . Taking a closer…

jasona 3 Jan 2011 • 3 min read

virtual platforms , android , boot loader , SystemC , ARM , debugging , linux , kernel

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