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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Tracing TLM 2.0 Activity in an ESL Design – Part 3

Last time I discussed how to use –sctlmrecord to produce an SST2 database of TLM…

• 7 min read
TLM , simvision , System Design & Verification , ESL

e Coding Made Easy with the “DVT” Integrated Development Environment

Specmaniacs everywhere should be aware of a great, full-featured integrated development…

• 6 min read
IEEE 1647 , SystemVerilog , eclipse , Specman , CDNLive , Functional Verification , OVM , OVM e , OVM SV , e , specman elite , AMIQ , eRM

It's Not Too Early to Think About DAC 2009

Even though it's still a couple of months off, it's not too early to think about…

• 1 min read
DAC 2009 , System Design and Verification , hardware-dependent software

OSCI Launches Video Tutorials for TLM 2.0

Cadence is one of the sponsors of a series of Open SystemC Initiative (OSCI) TLM…

• less than a min read
Intel , System Design and Verification , OSCI , TLM 2.0 , SystemC , interoperability , Modeling

Using Macros for Repetitive Coding Tasks

For this post welcome guest blogger Hilmar van der Kooij. Hilmar is a Cadence Application…

• 5 min read
Specman , Functional Verification , tech tips , OVM , OVM e , Coverage-Driven Verification , team specman , Aspect Oriented Programming , macros , AOP

Some SystemC Perspectives - An Interview with Vincent Motel

I sat down with Vincent Motel recently, a long time Cadence employee, and one of…

• 7 min read
OVM , C-to-Silicon , System Design & Verification , SystemC: OCSI

Performance-Aware e Coding Guidelines – Part 5

In this last segment of the series on performance-aware coding, allow me to share…

• 2 min read
IEEE 1647 , performance , events , Specman , Functional Verification , API , tech tips , OVM , OVM e , e , temporal expressions , OVM-e , specman elite , IES , IES-XL

Quick Tip - New Home For the "SVM" Docs

FAQs: What happened to the "SVM" documentation, and to SVM in general? Has SVM been…

• 1 min read
IPCM , Functional Verification , OVM , SVM , Incisive , eRM

CtoS support of Multiple Clocks

In a previous blog entry we discussed C-to-Silicon’s (CtoS’s) ability to support…

• less than a min read
High-Level Synthesis , CTOS , clock , System Design & Verification , SystemC , C-to-Silicon Compiler , clocking

Totally Off Topic: It's A Girl!

Allow me to digress from EDA subjects to herald the birth of my first child! …

• less than a min read
baby , Functional Verification , team specman , girl

Embedded Software on the Virtual Platform: Analog or Digital?

One of the things I learned when Verisity purchased Axis was the difference in mindset…

• 4 min read
Specman , virtual platform , System Design and Verification , analog , Enterprise Manager , waveform , functional coverage , ISX , check pointing , Jason Andrews

The Cadence ESL Machine Keeps Building Momentum!

Last week EDN named Palladium DPA a 2009 EDN Innovation Award Winner , and C-to-Silicon…

• 3 min read
System Design and Verification , Palladium , EDN , C-to-Silicon , EDN Innovation award

Performance-Aware e Coding Guidelines – Part 4

Specman 8.2s3 contains a new API to the sequence driver that enables users to improve…

• less than a min read
IEEE 1647 , performance , Specman , Functional Verification , API , tech tips , OVM , OVM e , e , OVM-e , specman elite , sequences , IES , IES-XL

C-to-Silicon Support of Concurrent Processes

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to C …

• less than a min read
High-Level Synthesis , CTOS , TLM , System Design and Verification , SystemC , ESL

Industry Discussion about High Level Synthesis

Many of you know that Richard Goering has joined Cadence and now writes a blog called…

• less than a min read
High-Level Synthesis , CTOS , TLM , System Design and Verification , Richard Goering , incisive c-to-silicon

Survey Results For "Booth-Centric" vs. "Paper Centric" Shows

In my last post I shared how my annual tour of the tour of the ESC show floor inspired…

• 2 min read
events , DAC , Specman , CDNLive , Functional Verification , CDNLive San Jose 2008 , ESC , DVcon , Xuropa

Performance-Aware e Coding Guidelines – Part 3

The constraint solver is a powerful and fun to use tool. Actually, it is so much…

• 1 min read
performance , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES , IES-XL

Homeschoolers Hungry for Technology

Over the weekend I attended the 2009 Minnesota Homeschool Conference in downtown…

• 4 min read
System Design and Verification , Lego , mindstorms NXT

Tracing TLM 2.0 Activity in an ESL Design – Part 2

In my last post I discussed two ad hoc approaches for tracing TLM 2.0 activity in…

• 4 min read
System Design and Verification , TLM 2.0 , George Frazier , SystemC , TLM 2.0 Trace

Another New Blog About the e Language

We are compelled to briefly interrupt Efrat's excellent series on Performance-Aware…

• less than a min read
IEEE 1647 , Specman , Functional Verification , e , OVMWorld

Verification of AUTOSAR Software Using a SystemC Virtual Platform

[Please welcome ISX R&D team member Markus Winterholer back to the Team ESL blog…

• 2 min read
AUTOSAR , BSW , System Design and Verification , RTE , SystemC , VFB , ISX

ESC and "Booth-Centric" vs. "Paper Centric" Shows

Last Wednesday I walked the floor of the Embedded Systems Conference (ESC) , with…

• 2 min read
events , DAC , CDNLive , Functional Verification , ESC , DVcon

Performance-Aware e Coding Guidelines – Part 2

Building on Part 1 where I talked about the “do’s and don’ts” of List performance…

• 2 min read
performance , IntelliGen , Specman , Functional Verification , tech tips , OVM e , e , OVM-e , specman elite , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Observations From the Embedded Systems Conference

Yes, there was another Embedded Systems Conference this year. Several "multi-year…

• 2 min read
Embedded Systems Conference , RTL , System Design and Verification , ESL

EDN's 19th Annual Innovation Awards

Two of Cadence system D&V products have been selected as the finalists for the EDN…

• 1 min read
System Design and Verification , Palladium , EDN , dpa , C-to-Silicon Compiler

C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

Some customers have inquired if C-to-Silicon Compiler (CtoS) is a “Low Level” Synthesis…

• 1 min read
High-Level Synthesis , CTOS , TLM , high-level synthesis adoption , RTL , System Design and Verification , TLM 2.0 , C-to-Silicon , SystemC , C-to-Silicon Compiler , ESL , architect

Is ESL changing EDA? Absolutely!

Geoffrey James's recent article provides a succinct description of several important…

• less than a min read
DAC , Estimation Planning , TLM , RTL , System Design and Verification , Synthesis , ESL

Performance-Aware e Coding Guidelines - Part 1

[Team Specman welcomes back Methodology R&D leader Efrat Shneydor to present a 5…

• 1 min read
IEEE 1647 , performance , IntelliGen , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES-XL
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