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In fourteen posts in that many weeks, the IC Packagers team has tried to live by the motto that Tyler spelled out in the first post of the series, "We'll try to cover all the topics that might interest you as we go, looking at a new area every week." Each post in the IC Packagers series, all written by Tyler except one written by Monika, talks about a pertinent topic giving us 'packagers' something useful and interesting. The topics for the post are selected carefully, based on queries that we receive through formal processes or through interactions with users. We also browse through what users are asking in our technical forums.
In this, the fifteenth post, we will talk about six broad steps of IC packaging using Cadence® SiP tools.
First thing first, you are starting with a new design and need to create a die package and get your dies in. We will spoil you with choices. You can import an existing Ball Grid Array (BGA) using the text-in wizard. You can also easily create your own in real-time or choose an off-the-shelf package from other vendors. Same goes for the die; use the Die Text-In wizard to import die data in a spreadsheet format; import DXF or GDS from the IC design tool and create a die from geometry; or, opt for a die abstract to communicate with the IC tool across platforms. Once the package and die are in place, use Cross Section Editor to view and edit the layout cross-section. You can modify most attributes by entering a new value in the appropriate cell. You can also set up parameters for embedded component design and to set dynamic unused pad suppression. And, by the way, you can use technology files to easily create the cross-section without entering all the data.
So far so good. Now comes the constraints. Several nets in your design have higher currents and need a different line width; create a physical constraint set defining the width requirement. A critical net needs a specific line-to-line spacing different from the default; create a spacing constraint set defining spacing need. Or, maybe, you want to identify certain DRCs, say make an acute angle check for the clines entering pads in the design. You can do that too.
Next, comes placement and shapes. Begin by setting the rules. That's easy using the detailed spreadsheet configuration that controls the various component-to-component DFA spacing rules. What's even better, you can have different versions of the rules with different spacing requirements, if needed, to support the different assembly processes. Whether you want to add or expand/contract a shape, editing shapes is intuitive with the Shape Edit application mode. You can also update thermal and clearance properties (say, thermal spoke width and quantity, connection type, and clearance size) associated with Dynamic Shapes and that too on a per-layer basis. But it doesn't end there - you can then get a 3D view of your design and cross-probe the design between the 3D and 2D views.
And, here comes wire bonding! Things start looking real, and you say "now we are talking" as do the dies and BGAs. But before starting to connect your dies with the substrate, most probably you want to see the die stacks that may include various combinations of dies (both standard and co-design), spacers, interposers, and adhesives or epoxy layers necessary for the manufacture of die stacks. You will most probably even end up editing vertical dimensions, spacer and interposer material data, and flip-chip bump dimensional data. So, go ahead and use Die-stack Editor. Now, change to the Wire Bond Edit application mode. Like the Shape Edit application mode mentioned earlier, the Wire Bond Edit mode is also intuitive and easy to use - select an object, say a die pin, right-click, and choose an option, say, Add wire bond. And, while at it, you get access to a set of wire profiles compatible with bonding machines used by manufacturers. You will also definitely want to run Assembly Rules Checker to verify your package meets the bond wire’s physical and spacing requirements necessary for the part to be successfully manufactured and assembled. And, of course, you will love to verify your package using both 3D Canvas and 3D Viewer.
You are now in the route phase. You will create BGA pad fanouts or pin-escapes - in SiP tools you will use automatic features. You can choose to use the Auto Fanout feature or use Via Structures for more control. Use the Flow Planning feature to manage connections abstracted as bundles and perform AiBT trunk routing. Fine-tune routing manually by using Push, Shove, Plow, and Scribble Mode. And, if you have differential pairs, you might also add return path vias. Most probably, your's is a high-density interconnect (HDI) design and you will use the Miniaturization Constraint Manager-driven solution for setting up the clearance matrix associated with HDI technology, such as microvia-to-microvia and microvia-to-core via spacing rules.
Finally, it's the post-processing/documentation phase. You will add numbers and net names to the bond fingers and label BGAs. But that is easily done using the options in Manufacture - Documentation. You might create three-dimensional documentation or graphics to transfer data back to an MCAD system; for instance as DXF files. Or you might want to exchange stream data using GDSII format. You can, of course, create artwork files, but what's more, you can export IPC 2581 files in the XML file format to help in the manufacturing of substrate or to start a new design.
If any or all of the broad steps interests you and you want to try out the steps using a sample database, click here for a Rapid Adoption Kit with detailed step-by-step procedures and sample databases.
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