• Discussion

  how to import virtuoso gds output in to APD (advanced package designer)

  19701 views
  7 replies
  Latest over 18 years ago
  by archive
• Discussion

  Manipulating Unpacked Arrays using DPI Locked

  14073 views
  0 replies
  Started over 18 years ago
  by archive
• Discussion

  Resolving aborts after "analyze abort -compare" Locked

  2683 views
  1 reply
  Latest over 18 years ago
  by archive
• Discussion

  How to hilight nets or symbols

  12279 views
  0 replies
  Started over 18 years ago
  by archive
• Discussion

  Share Queue between class? Locked

  14970 views
  2 replies
  Latest over 18 years ago
  by archive
• Discussion

  Hello ihdl users. help required - verilog to schematic conversion Locked

  1478 views
  1 reply
  Latest over 18 years ago
  by archive
• Discussion

  extracta command line for - Etch Length by Pin Pair

  1063 views
  0 replies
  Started over 18 years ago
  by archive
• Discussion

  Cadence website low power page Locked

  13022 views
  1 reply
  Latest over 18 years ago
  by archive
• Discussion

  Richard Goering's blog on CPF Locked

  440 views
  0 replies
  Started over 18 years ago
  by archive
• Discussion

  Low Power tip of the Week: Special cells fro advanced low power techniques Locked

  12987 views
  0 replies
  Started over 18 years ago
  by archive
• Discussion

  warning: "could not fit symbol" Locked

  2956 views
  3 replies
  Latest over 18 years ago
  by archive
• Discussion

  callbacks in Virtuoso? Locked

  13156 views
  0 replies
  Started over 18 years ago
  by archive
• Discussion

  Allegro Padstacks; Defined Geometry vs. Flash Locked

  14563 views
  3 replies
  Latest over 18 years ago
  by archive
• Discussion

  About Design Attributes

  12907 views
  1 reply
  Latest over 18 years ago
  by archive
• Discussion

  Using .sp file for connector in SigXP Locked

  14319 views
  4 replies
  Latest over 18 years ago
  by archive