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  De-emphasis level in Macromodel Locked

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  board outline segments merge Locked

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  modeling a constraint for a signal that is only high once (ever) Locked

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  Change names in FE Locked

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  via xy report Locked

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  autosilk coflict with pin? Locked

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  Cross Probe between Concept and Allegro during placement Locked

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  Property transformations Locked

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  Dptol never goes green. Locked

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  Cadence IC5.141 with NCSU design kit 1.2 or 1.5 Locked

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  memorizing last known gui size in FE Locked

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  Allegro Design Entry CIS junction (dot) too small Locked

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