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I came up with the following LVS error concerning all transistors with
multiplicity factor m (NOT with just fingers and no multiplicity factor
in contrary) in my design.LVS debug environment details give the
following description : FET1comp has mismatched parameter(s):"w" layout: 1.5e-05 schematic: 7.5e-06
Let me be more specific.For the above description,in my
design i have a transistor with Wtotal=15um and multiplicity factor m=2
(thus 2 fets in parallel with 7.5um width each),well,assura can make the
correct computation for the layout and it shows the actual Wtotal but
it cannot estimate the correct value for the Wtotal for the side of the
schematic (it seems considering m=1 always independent from the value i
have set in the fet properties).Is there any way to get rid of this
error (with some switch under Modify avParameters menu for example) or i should make any change to the compare rules file to the respective funtion?I show you the properties of the nfet :
Width Single Finger : 7.5u
Width All Fingers :7.5u
Thus,Wtotal=15u as i mentioned earlier.
The following lines contain the part of the compare.vldb file with the respective section for the FET1comp function :
procedure( FET1comp(m1, m2)
("l" "abs_comp" "if(BentGate<0.5 then hgp else hgp7)")
("w" "abs_comp" "if(BentGate<0.5 then hgp else hgp7)")
unless(getValCase(m1 "m") m1->m=1)
unless(getValCase(m2 "m") m2->m=1)
unless(getValCase(m1 "idg") m1->idg=0)
unless(getValCase(m2 "idg") m2->idg=0)
if( (m1->idg && abs_comp(m1->idg 0 0.5)) then
m1->w = getValCase(m1 "w") * getValCase(m1 "m") )
if( (m2->idg && abs_comp(m2->idg 0 0.5)) then
m2->w = getValCase(m2 "w") * getValCase(m2 "m") )
unless(getValCase(m1 "bentgate") m1->bentgate=0)
unless(getValCase(m2 "bentgate") m2->bentgate=0)
BentGate = m1->bentgate + m2->bentgate
genericcomp("FET1comp" m1 m2 paraminfolist)
I must say that i use IBM cms9flp pdk finally if somebody didn't notice that on the post subject.Also Cadence IC 6.1.3 under opensuse 11.1 operating system 64-bit.
Can somebody give me a helpful hint how to solve this problem?Changing all transistor to bus will be a painful procedure for me and i want to avoid it if possible.
Thanks in advance for any helpful answer and if more clues are needed ask me to post them here.
Hi jimitoThis indeed seems like a small bug in the compare rules. IBM pdks have long compare rules file and so I think ultimately you might have to request for more support from your local IBM or Cadence support centre.Would you please check the cdf info for the cell to see if the multiplicity property is really "m" or some other name (e.g. mfac, mf, etc)?In ciw, go to "Tools->CDF->Edit CDF". ThanksQuek
In reply to Quek:
I checked the menu you suggested but i didn't find any information...
In reply to jimito13:
Hi jimitoSuppose the multiplicity problem is for a schematic cell named "nfet123" in library "myTechLib". Would you please help to execute the following cmd in ciw and upload the output file "cell.cdf"? Please use the upload function, not cut and paste.cdfDump("myTechLib" "cell.cdf" ?cellName "nfet123" ?level 'base)Please also provide the following info:terminal>assura -Wterminal>virtuoso -WPlease also upload the "design.vlr" file in the lvs run directory.ThanksQuek
At first thanks for your interest to my problem.I run the command in ciw but the cell.cdf output file is empty(!),so there is no reason to upload.What can we see from this file if it had something in it?
The file with .vlr extension is IBM confidential and i can't post it or upload it anywhere...Guide me with a similar file that apparently you have as well and i will give you the feedback for the thing that we must know from that file.
Output from the 2 commands in terminal :
Hi jimitoI am trying to find out the actual cdf parameter name for the "multiplicity" parameter in the properties form. Not very sure why your cdfDump is empty. : ) Would you please help to do the following?a. In the ciw (this is the first window that shows up when Virtuoso starts up), go to "Tools->CDF->Edit CDF"b. Use the "Browse" button and select the transistor that has the problem.c. The cdf form shows upd. In the top right hand corner, enter a filename and press the "CDF dump"Hopefully the gui will be able to help you generate a proper file. Please upload the file. ThanksQuek
I did the procedure you mentioned above but at first i am not given the ability from the gui to choose the transistor that has the problem but i can choose the schematic or layout view,so doing this the cell.cdf file has some parameters with "nil".Doing what you suggested for a single nfet of the cms9flp library,the actual cdf parameter name for the "multiplicity" parameter is "m".What is exactly the CDF??
And a final and a little bit irrelevant question with the above.Virtuoso makes sometimes a sound like a beep.I know how to shut it down,but i want to do it permanently...Do you know a command that i can write in a file (is this file .cdsinit?) to do it?
Thanks in advance.
jimito13And a final and a little bit irrelevant question with the above.Virtuoso makes sometimes a sound like a beep.I know how to shut it down,but i want to do it permanently...Do you know a command that i can write in a file (is this file .cdsinit?) to do it?
I do this in .cdsenv, but you can easily change the syntax if you want it to be in .cdsinit:
ui beepVolume int -100
Hi jimitoCDF refers to Component Description Format. It contains the parameter that your instances has and controls which parameters go into the netlist. Since "multiplicity" does indeed has parameter name "m", it is not a matter of indentifying a custom mfactor name to Assura. It would be quite tough to debug without a testcase so it would be good if you can contact your local Cadence/IBM support for this problem.Best regardsQuek
Thank you very much for your effort to help me with this problem.This is the last step,to contact my IBM representative...Hope they have a solution.
Well,i contacted IBM and the first answer was this :
"In layout, if the pcell has multiplicity parameter set to
>1, then there will be a layer called MULTI DEV surrounds the pcell.
This will prevent the LVS from combining devices in the layout"
I replied to them saying that i can't find that layer anywhere and asked them to guide me to find it and the final anwer was this :
"It appears that in cms9flp Assura VLDB mode LVS does
have some problems recognizing multiplicity from the schematic side.
Assura CDL mode and Calibre LVS will both recognize multiplicity
properly. I will investigate further on the Assura VLDB mode LVS. Please
use CDL mode LVS or Calibre LVS if you can"
The problem is the following,trying to use CDL the error vanishes but others concerning devices and nets come up that don't make sense since my testcase is one nfet so if there was such an error it could be visible easily.Other problem is that we don't have calibre and the time to learn how to use it until the tape-out that is in a few days!
Finally i decided that i must change to bus mode naming for the transistors and the problem is solved partially since some nets get strange name like net33<0> and i can't even check n' save my schematic...
I am in desperate condition,please if somebody knows a way to get rid of this damn problem,let him do it,i will appreciate it.
Thanks in advance.
In reply to skillUser:
Hi YiassouJust as what Lawrence has suggested, I think it would be good if you can file a service request to your local Cadence support. If your pcell does not have the MULTI DEV layer even after setting multiplicity parameter to be greater than 1, then it seems to be a pcell problem. Would it be possible to resolve the problem by manually creating a MULTI DEV layer over the appropriate pcells? Best regardsQuek
Thanks for your interest and your replies :-) Can you please guide me to set up the MULTI DEV layer?From where it should be present normally,from the cadence virtuoso XL/assura GUI or from a file?If possible show me a part of a correct file if it must be configured from there.And a final question,what we mean saying "pcell"?
Thanks in advance for any hepful suggest.
Hi JimitoPcell refers to "parametrized" cells. This means that the cell layout can change according to the changes made in the properties form. The cells in your IBM pdk are pcells which you can used in your layout. Please go to LSW, set all layers as valid and check if there is a layer named "multidev" (my guess). : ) Create a rectangle that covers your cell using this layer. Now re-run lvs to see if it makes a difference.I would also strongly suggest that you contact Cadence support now to get more help on troubleshooting this.Best regardsQuek
I have already searched for this layer but i can't find it and i have already mentioned it in previous e-mail to IBM's support,but they didn't give any feedback except from admitting that there is a bug in VLDB mode LVS...The main problem is that i am not talking myself directly with IBM and my professor that does this insists that i must do the following : wherever in schematic i have devices with m factor to substitute them with m parallel single devices in order to pass LVS.But this is going to cost a lot of time i think.Anyway,i will see how to deal with this.Thanks again for your precious help.