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Hi, I am using ADEXL to conduct MC statistial simulations.I know it is easy to do MC simulation on model paramters like Vth by adding statistical distribution in model card. however, here I need to statistically simulate instance parameters like Leff, width of the nmos... is there any way to do it？ thank You in advance
Ps. Is there anyway to do MC simulations on other variables like power supply ?
you can vary any parameter you want by just providing a statistic section for it inside an included model file.
For example: Instead of giving 1k to an analogLib resistor you write 1k*x and create a statistic for "x".
The problem is, you want use several instances of that res and apply a different "x" variation. In that case you need to pushthe "x" into a subcircuit, means you need to create an additional schematic/symbol for that resistor cell. Placing the resistor and pins in the schematic and parameterizing the value with pPar("res")*x. The you create the symbol for it.
If you have a support account you can check:
In reply to Marc Heise:
Thank you so much for your help, Marc!
I have one more question about providing a statistical section for one instance parameter? like the width of an NMOS fet....Should I assign it in the process section or mismatch section?
Is it use process statistial format to define it as follows:
vary width dist=gauss std=0.1 percent=no
In reply to reliability:
That depens on what you are planning to vary.
Process: Your device is probably produced on more than one wafer. No wafer is like the other. The production "process" will vary. This is captured by the process variation.
Mismatch: Now that device is existing more than once on that same wafer. But also here you have some kind of variation depending on where the device is located on the wafer. This is captured by the mismatch variation.
Now you can apply both or just one of them, realy depends on what you are looking for.
For a resistor the process variation can be around +/- 20% and the mismatch +/-5% ( depends on the foundry).
Process variation is usally larger than mismatch variation.
Depends what you want to vary, both or one of them.
Process...variation of devices on different wafers.
Mismatch...variation of devices on same wafer.
If you select both, mismatch is applied ontop of process.
( hmm.. kind of double post. Got an error after the first message and expected it to be lost))
thank you very much for your detailed answer, Marc!
Another question is Width of the devices is a design variable is unlike threshold voltage which is defined in the model card. I tried to add the process/mismatch for width/VDD distribution in the model card, but my output does not change at all...Actually if i change the width/VDD by sweeping simulation instead of MC simulations , the output actually changes a lot... it seems to me the the statistical sentences controling the distribution of width is not affecting the MC simultion.....Do you know the answer to that?
Without some hard data (netlist, model, log) there is not much I can do.