Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Hi, I am using ADEXL to conduct MC statistial simulations.I know it is easy to do MC simulation on model paramters like Vth by adding statistical distribution in model card. however, here I need to statistically simulate instance parameters like Leff, width of the nmos... is there any way to do it？ thank You in advance
Ps. Is there anyway to do MC simulations on other variables like power supply ?
you can vary any parameter you want by just providing a statistic section for it inside an included model file.
For example: Instead of giving 1k to an analogLib resistor you write 1k*x and create a statistic for "x".
The problem is, you want use several instances of that res and apply a different "x" variation. In that case you need to pushthe "x" into a subcircuit, means you need to create an additional schematic/symbol for that resistor cell. Placing the resistor and pins in the schematic and parameterizing the value with pPar("res")*x. The you create the symbol for it.
If you have a support account you can check:
In reply to Marc Heise:
Thank you so much for your help, Marc!
I have one more question about providing a statistical section for one instance parameter? like the width of an NMOS fet....Should I assign it in the process section or mismatch section?
Is it use process statistial format to define it as follows:
vary width dist=gauss std=0.1 percent=no
In reply to reliability:
That depens on what you are planning to vary.
Process: Your device is probably produced on more than one wafer. No wafer is like the other. The production "process" will vary. This is captured by the process variation.
Mismatch: Now that device is existing more than once on that same wafer. But also here you have some kind of variation depending on where the device is located on the wafer. This is captured by the mismatch variation.
Now you can apply both or just one of them, realy depends on what you are looking for.
For a resistor the process variation can be around +/- 20% and the mismatch +/-5% ( depends on the foundry).
Process variation is usally larger than mismatch variation.
Depends what you want to vary, both or one of them.
Process...variation of devices on different wafers.
Mismatch...variation of devices on same wafer.
If you select both, mismatch is applied ontop of process.
( hmm.. kind of double post. Got an error after the first message and expected it to be lost))
thank you very much for your detailed answer, Marc!
Another question is Width of the devices is a design variable is unlike threshold voltage which is defined in the model card. I tried to add the process/mismatch for width/VDD distribution in the model card, but my output does not change at all...Actually if i change the width/VDD by sweeping simulation instead of MC simulations , the output actually changes a lot... it seems to me the the statistical sentences controling the distribution of width is not affecting the MC simultion.....Do you know the answer to that?
Without some hard data (netlist, model, log) there is not much I can do.