how to pass array of parameters through CDF down to a verilogA code?

Ali,

Make the value in the CDF "[0 0 1 0]". It needs to be netlisted with spectre's vector syntax, rather than the VerilogA vector syntax.

I just tried this, and it works fine.

Andrew.

 Hi Andrew,

Thanks for reply.

Here is my verilogA code. When I enter "[0 0 1 0]" (as you sugessted) spectre complains about the missing comma between values.

Giving  "[0, 0, 1, 0]" passes the compiler and then transient simulation shows wrong values for the output voltages as [ 589.3E6,  9.223E-297, 0.0, 0.0] .

I tried it on IC6.1.4-64b.500.9 ,"v2009.4_23.21"

Regards,

Ali

`include "constants.vams"
`include "disciplines.vams"
`define LENGTH 4

module vbus(A);
output [`LENGTH-1:0] A;
voltage [`LENGTH-1:0] A;

parameter real vdc[`LENGTH-1:0] =[0, 0, 0, 0];

analog
begin
        generate i (`LENGTH-1,0)
        begin
                V(A[i]) <+ vdc[i] ;
        end
end

endmodule

Ali,

You misunderstood. The VerilogA code needs to use {0,0,1,0} syntax, but in the CDF you'll need to define the default as [0 0 1 0] (no commas, although commas are tolerated at the moment - but you get a warning about them not being supported in the future). Also, when you instantiate the block, with a different value, you'd need to specify it with square brackets. To illustrate what I mean, here's some VerilogA:

 `include "disciplines.vams"

module blah (op,ip);

output op;
input ip;
electrical op,ip;

parameter real vdc[3:0]={0,0,1,0};

analog begin

   V(op) <+ vdc[2]*V(ip);

end

endmodule

and here's the corresponding spectre netlist:

 //

I1 (o1 i1) blah vdc=[2 2 2 2]

v1 (i1 0) vsource type=sine freq=1M ampl=1

ahdl_include "blah.va"
tran tran stop=2u

 Awesome, Worked just fine.

Thanks,

Ali

 Andrew,

I ran into the same problem and I tried out your solution. It did not work and I wonder if the solution is now different with cadence 6.1.5 ?

 // VerilogA for zakir_sim1, bb_prereg_ldo, veriloga

`include "constants.vams"
`include "disciplines.vams"

module trim3bits(sel);
output [2:0] sel;
electrical [2:0] sel;

parameter real trim[2:0] ={0,0,0};

analog begin

V(sel[2]) <+ trim[2]*1.1;
V(sel[1]) <+ trim[1]*1.1;
V(sel[0]) <+ trim[0]*1.1;

end

endmodule p, li { white-space: pre-wrap; }

Begin Incremental Netlisting Oct 8 16:44:23 2013

"ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I6' in design 'zakir_sim1/test1/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"

"ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I6' in design 'zakir_sim1/test1/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"

"ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I6' in design 'zakir_sim1/test1/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"

"ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I6' in design 'zakir_sim1/test1/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"

"ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I6' in design 'zakir_sim1/test1/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"

End netlisting Oct 8 16:44:23 2013

ERROR (OSSHNL-514): Netlisting failed due to errors reported before. Netlist may be corrupt or may not be produced at all. Fix reported errors and netlist again.

...unsuccessful.

That looks as if there's a mismatch between the pins on the symbol and the pins on the veriloga view. Or there's something wrong with the CDF.

Andrew.

The above solution works when we actually pass parameters since the default parameters {1,2,3,4} are overridden by the passed parameters [1 2 3 4]. Generally I do not override parameters if I want to use the defaults. But due to this syntax problem I have to always pass parameters for the simulation to work.

Is there a fix planed(to sync syntax of veriloga with spectre or viceversa)?

Thanks and have a Wonderful day,

Narasimhan Rajagopal

Narasimhan,

There's not a need for spectre and veriloga to be aligned in terms of syntax, but there is a CCR for this to be handled correctly in the CDF - CCR 1094193. However, there is no plan to fix this - maybe that would change if more people asked for this via customer support.

Regards,

Andrew.

Thanks Andrew. I will notify this to our EDA team. They will take it up with Cadence support on a priority basis.

Narasimhan

hi Andrew, I am facing the same issue: "ERROR (SFE-874): "input.scs" 1087: Unexpected block statement "{"." Has this issue been resolved yet? Can Spectre now handle VerilogA arrays such as {1,2,3,4}. Thank you.