Convert schematic to Verilog file

Either Tools->NC Verilog (from the CIW), or  Launch->Simulation->NC Verilog (from a schematic).

Andrew.

Any shell command for generating verilog code from schematic hierarchically from top cell to bottom

 Set it up in the UI as described above, and then you can do:

si -command netlist -batch pathToRunDirectory

Andrew.

 I am following following procedure for creation oa2verilog  

Open a shell from the library manager using File->Open shell window. This shell will be initialized with the necessary environment variables for the next step.

In the new shell use:

oa2verilog -lib <name of library> -cell <name of cell> -view schematic -verilog <name of cell>.v -recursive

Substitute the lib name and cell name for the specific cell to netlist.

This is limited to a cell without hierarchy

 I want generate it for hierachy Could you please help on this.

Regards,

Rambabu

I already explained how to do this with the Verilog netlister. oa2verilog is much lower level and does not support all of the complex control that the OSS Verilog netlister does. I would not recommend  you trying to use oa2verilog (it doesn't have the concept of switch and stop list, for example, nor does it support config views).

Andrew.

And you can tell this by the very small amount of coverage of oa2verilog in the documentation (search in cdnshelp and you'll see what I mean).

Andrew.

Hi all,
This might be the most comon problem/task for ASIC engineers. I need a script that will generate a top level module for 'n' verilog modules (in 'n' files)

Say I have A.v & B.v. The script should generate a ABTop.v such that

module ABTop(
clk
:
:
);

input clk;
input (etc etc)
:
:
output (etc etc)
:
:

A A_i (
.clk (clk)
:
:
:
);

B B_i (
.clk (clk)
:
:
:
);

endmodule

if there is any shell command for automation, please suggest me.

Regards,

Rambabu

The Verilog netlister (using "si") can do this. This is covered in solution 1839821 . The quick executive summary is that you can put:

vlogifCompatibilityMode = "4.0"

in your .simrc (or .cdsinit if using Virtuoso). It will then create a single Verilog netlist (concatenated from the individual pieces that the verilog netlister normally produces).

Regards,

Andrew.

 Thank you Aandrew for your help

Regards,

Rambabu