Convergence Issue with verilogA model

 Hi, (some weird text appers below and i dont know what that is, my post starts with : I am sim......)

I am simulating 12 bit segmented SAR ADC with comparator in Verilog A. I have read several posts on achieving convergence like relaxing tolerances/specifying cmim etc. In a 12 bit ADC my LSB is around 250uV and I can’t afford to relax the tolerances further from their default values.

Problem:

Anyway the problem is not with my foundry model circuit instances, nothing wrong with the circuit netlist. I face convergence problems at the output of Verilog A comparator model. And I need to know how to fix the comparator code to avoid convergence issues. When I replace Verilog A comparator with transistor based design, no convergence problems are flagged.

But I have to run MC simulations and I don’t want to include the spread of comparator in my ADC accuracy plots for now, so it is crucial that I use Verilog model for comparator.

Although issues are flagged (error requirement were not satisfied because of convergence difficulties), for nominal run I don’t get convergence problem. But during MC simulations when a 200th simulation fails to converge, it translates to enormous wastage of time.

I have attached pdf presentation containing snapshots of my problem.

Fig 1 shows the entire circuit schematics

Fig 2 shows the comparator block and the node where convergence issue is reported

Fig 3 shows the Verilog code for comparator

Fig 4 and 5 show the snapshots of output log files which I have commented

So the problem is with the Verilog code of comparator. Can we change the Verilog code to achieve convergence? If yes then what should I change? If no then what should I do?