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Digital Pot: MOS as a logic switch

ctayers

Virtuoso IC6.1.5.500.9

For a class I need to build a digital potentiometer.  To do this Ive seen schematics where a MOSFET is used as a logic gate.  I attached an image really similar to my schematic.  I can get the gate control wires to see VDD, but Im not sure that I know what MOS to use (virtuoso symbol, then simulate), or how to size it.   When I apply VH=10 VDC, I would think if it was working correctly you would see a corresponding voltage on VW that works as if a voltage divider was activated at the MOS that is turned "on".  However VW seems stuck at 0.5V or so.

Can anyone help please?

Parents

  • Dear Cyrus,

    > Do you mean like this? where A is the control signal and then you can have some In and Out?

    Yes. This is the structure I was suggesting. A and Abar are complementary CMOS signals.

    > Edit: i used 100 mV input.  But with 2.5 V as the control signal to A, the output is always

    > 100 mV, even if I make A=0, and A`=2.5. Can you help?

    Are you performing a DC analysis to examine the output voltage with 100 mV input voltage? If you are performing a DC simulation, the steady state output voltage may be the same as the steady-state input voltage - even if the switch is in its non-conducting state. A more appropriate simulation to run to study the transfer function of the structure is to examine its impedance as a function of the two states of the control signals A and Abar over the expected ranges of the input and output voltages. A possible simulation methodology follows (there are others I am sure).

    Set CMOS signals A and Ab to one logic state

    Set the input node to an ideal current source with an AC magnitude of 1 and set the output to an ideal voltage source with a DC value of VDC.

    Run a set of AC analysis as VDC is varied over the expected range of the input and output voltages

    Measure the voltage across the input current source to determine the impedance seen at the input port for each value of VDC.

    Set CMOS signals A Ab to their opposite logic states and repeat the prior set of simulations and measurements.

    I assembled a quick schematic of such a switch simulation and have plotted the input resistance (node vs)  for ranges of output voltages between 0 and 800 mV in 200 mV increments with the switch signals vsw/vswb in their set of "switch on" and "switch off" states in Figures 1, 2, and 3 respectively. I hope this helps.

    Shawn

    example_switch_simulation.pdf

Reply

  • Dear Cyrus,

    > Do you mean like this? where A is the control signal and then you can have some In and Out?

    Yes. This is the structure I was suggesting. A and Abar are complementary CMOS signals.

    > Edit: i used 100 mV input.  But with 2.5 V as the control signal to A, the output is always

    > 100 mV, even if I make A=0, and A`=2.5. Can you help?

    Are you performing a DC analysis to examine the output voltage with 100 mV input voltage? If you are performing a DC simulation, the steady state output voltage may be the same as the steady-state input voltage - even if the switch is in its non-conducting state. A more appropriate simulation to run to study the transfer function of the structure is to examine its impedance as a function of the two states of the control signals A and Abar over the expected ranges of the input and output voltages. A possible simulation methodology follows (there are others I am sure).

    Set CMOS signals A and Ab to one logic state

    Set the input node to an ideal current source with an AC magnitude of 1 and set the output to an ideal voltage source with a DC value of VDC.

    Run a set of AC analysis as VDC is varied over the expected range of the input and output voltages

    Measure the voltage across the input current source to determine the impedance seen at the input port for each value of VDC.

    Set CMOS signals A Ab to their opposite logic states and repeat the prior set of simulations and measurements.

    I assembled a quick schematic of such a switch simulation and have plotted the input resistance (node vs)  for ranges of output voltages between 0 and 800 mV in 200 mV increments with the switch signals vsw/vswb in their set of "switch on" and "switch off" states in Figures 1, 2, and 3 respectively. I hope this helps.

    Shawn

    example_switch_simulation.pdf

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