Digital Pot: MOS as a logic switch

Dear Cyrus,

> I would think if it was working correctly you would see a
> corresponding voltage on VW that works as if a voltage divider was
> activated at the MOS that is turned "on".  However VW seems stuck
> at 0.5V or so.

The basic topology you provide is a viable means of providing a programmable resistive ladder. However, there are a number of potential issues to consider. The specific circuit details are not provided in your diagram - so I will need to rely on your knowledge as to which of these are or are not relevant - sorry!

1. Is it possible that with the MOS device models you are using the 10V VH signal voltage exceeds the breakdown voltage of the MOS transfer gates or is causing excessive gate leakage? If it exceeds the breakdown voltage or the gate leakage is high, most likely all 100 transfer gates will present a finite resistance to node VW, and the resistance will not change significantly with the decoder output code. Have you examined the use of a lower voltage for VH - say something less than Vcc powering the decoder (I am assuming Vcc powers the decoder)? In essence, study the output voltage at VW as a function of code words for VH set to Vcc, 2V, 4 V, 10V to determine if you are observing a leakage or breakdown effect.

A few other questions or thoughts...

2. What is the impedance of node VW? Does it represent an infinite impedance or is there a finite resistance to ground?

3. I am also assuming node VL is grounded - is this true? It sounds as if it as you are observing a voltage less than 10V (0.50 V) at node VW.

4 Often in this topology the "transfer gates" are formed as a parallel combination of a pmos and nmos gate whose gates are driven by complementary signals. This minimizes the variation in their net drain source resistance as the voltage at their drain and sources vary. If the transfer gates are only nmos, the variation in their rds as VW varies will be significant. This is likely mot your issue, but it can be effective at improving robustness of the ladder.

I hope these thoughts help you determine the issue!

Shawn

1. I tried your suggestion for the Potentiometer.  That works to increase device size and lower the input voltage to 100mV (probably I can reduce the device size now that I know what the problem was).

2. Im testing VW at open circuit currently.  In the future I think we will use a buffer op amp (Which we design) to help with output impedance.

3.  VL is grounded

4.  Would you have a quick link to such an example of a transfer gate? Those would come in very useful to build relay-like switches.  Basically I want to be able to turn a solid-state switch on and off with another voltage signal.  My NMOS W=15u, L=6u currently.  AMI05 process.

This has been very helpful!

Do you mean like this? where A is the control signal and then you can have some In and Out?

Edit: i used 100 mV input.  But with 2.5 V as the control signal to A, the output is always 100 mV, even if I make A=0, and A`=2.5. Can you help?

Dear Cyrus,

> Do you mean like this? where A is the control signal and then you can have some In and Out?

Yes. This is the structure I was suggesting. A and Abar are complementary CMOS signals.

> Edit: i used 100 mV input.  But with 2.5 V as the control signal to A, the output is always

> 100 mV, even if I make A=0, and A`=2.5. Can you help?

Are you performing a DC analysis to examine the output voltage with 100 mV input voltage? If you are performing a DC simulation, the steady state output voltage may be the same as the steady-state input voltage - even if the switch is in its non-conducting state. A more appropriate simulation to run to study the transfer function of the structure is to examine its impedance as a function of the two states of the control signals A and Abar over the expected ranges of the input and output voltages. A possible simulation methodology follows (there are others I am sure).

Set CMOS signals A and Ab to one logic state

Set the input node to an ideal current source with an AC magnitude of 1 and set the output to an ideal voltage source with a DC value of VDC.

Run a set of AC analysis as VDC is varied over the expected range of the input and output voltages

Measure the voltage across the input current source to determine the impedance seen at the input port for each value of VDC.

Set CMOS signals A Ab to their opposite logic states and repeat the prior set of simulations and measurements.

I assembled a quick schematic of such a switch simulation and have plotted the input resistance (node vs)  for ranges of output voltages between 0 and 800 mV in 200 mV increments with the switch signals vsw/vswb in their set of "switch on" and "switch off" states in Figures 1, 2, and 3 respectively. I hope this helps.

Shawn

example_switch_simulation.pdf

Ok thank you we are trying that out, I will post back if we get it to work.  Is your bulk connected to VDD for pmos and VSS for nmos? Typically we connect source to bulk in Schematic view but im not sure that works for exporting to a layout.

I had another question, do you know how to automatically generate a Layout from a schematic?  We are using NCSU_Techlib_ami06 process and OSU_stdcells_ami05 for the boolean logic gates.  I know how to use p-cells, but this layout will take days by hand and the class dosent provide any help on this.  I've been looking for a website that has steps for doing this in Virtuoso IC.1.5.500.9, but havent had much luck, even though I know there must be something.

Thank you