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Vth0 definition in scs file

BaaB

I am designing with library tsmcn65. I am having a problem understanding spectre circuit simulator  scs file. As you can see in the crn65gplus_2d5_lk_v1d0.scs or the image attached below, with a mosfet nch_na there are many Vth0 definitions.

So which one is used for normal simulation? How to choose or define it?
Are there some materials explaining about this?

Note from Moderator - Removed Image as it was sharing TSMC's IP which would have been in violation of your NDA with TSMC.

  • Andrew Beckett

    I removed the screenshot because it was sharing TSMC's IP which I doubt you are authorised to do, and certainly we should not have it on a Cadence web site.

    The answer is that these are binned models - depending on the width and length of your transistors, they will fit into one of the bins formed by the wmin/wmax and lmin/lmax ranges in each of the numbered bins. Once it's determined that, it will use whichever model from that bin (and hence that vth0).

    Regards,

    Andrew.

  • BaaB
    Thanks and sorry for the mistake. Does width and length are total width and length with number of fingers and multipliers or just of a single one? By the way, where can I find a detail talking about this?
  • Andrew Beckett

    It's the w and l as specified in the netlist (so the finger width and length, not total). Essentially it's based on the channel w and l and the rest is handled by the normal multipliers for parallel devices.

    Run <MMSIMinstDir>/tools/bin/cdnshelp and search for "binning". You'll find a section in the Parameter Specification and Modeling Features section of the Virtuoso® Spectre® Circuit Simulator and Accelerated Parallel Simulator User Guide which covers how it works.

    Regards,

    Andrew.

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