How to use PSS+PSTB or PSS+PAC to simulation the loop gain of the amplifier in the MDAC in each clock phases

The Periodic Stability analysis (pstb) does not give you the loop gain in each phase. It gives you the time-averaged loop gain over the whole period, which is what you really want. If you want the loop gain in a particular phase, you could run a transient, set up a stb analysis, and then specify the acnames and actimes parameters of the tran analysis to measure the loop gain at the times where each loop is closed. However, that is probably not what you want... pstb is more likely to be useful.

Similarly, Periodic AC (pac) gives you the time-averaged small-signal response to a small signal input over the period.

A couple of corrections from the document you referenced (there may be others, I just scanned it quickly):

• The iprobe does not "break" the loop. The loop remains closed at all times, which is the point of these analyses. It is the perturbation/measurement point for the loop gain
• You should no longer use cmdmprobe to measure differential and common-mode stability. Instead there is a superior component, diffstbprobe which copes with the loops not being balanced (i.e. if there is common-mode to differential-mode leakage or vice versa) and also allows the choice of whether you are measuring common mode or differential mode to be made on the analysis form, rather than on the component itself.

Regards,

Andrew.

Hello!

Andrew,

Thanks for your professional reply!

Now for my understanding, the Switched Capacitor Common Mode Feedback Cicuit (SC-CMFB), although operating in two different clock phases (the total capacitor connected in the loop is different in each phase), it makes the output common mode voltage to "jump" up and down around the desired value, to mimic the continues time one. The two different clock phases are relative to each other. So I think the "the time-averaged loop gain over the whole period" provided by Periodic Stability  analysis (pstb) is reasonable if we want to use pstb to assess the loop stability of the SC-CMFB.

But for the Multiplying DAC (MDAC)  circuit I referred in Fig. 1, it operates in two different clock phases and each phase has different function (phi1 is auto-zeroing, feedback factor is nearly one; phi2 is amplification, feedback factor is determined by C1/(C1+C2) ) . These two phases are not "coherent" like that of SC-CMFB.  In order to make sure this circuit is stable, I need to make sure this circuit is stable in each phase. So that's why I want to find some method to assess the stability of particular phase. 

However, the amplifier I used in the MDAC is a highly non-linear amplifier. So It's hard for me to specify a time to "represent" the amplifier in the transient simulation then use the method that you referred. So I want to use the pstb to analysis  "the time-averaged loop gain" within a particular phase.

But as you said "The Periodic Stability analysis (pstb) does not give you the loop gain in each phase ", pstb may be not OK for this purpose.

I really want your comments and suggestions !

Best,

Shen

Hi Shen,

OK - I'd not looked at the small diagram with the two phases indicated. You have two feedback loops - each switched by a different phase. You need to insert the iprobe (or diffstbprobe if it's differential - your Fig 1 only shows a single-ended amplifier) in the loop you're interested (you can have both components there and just pick the one you want when simulating). If the probe is at the output of the amplifier it would include the effects of both loops; if it was in just the loop for phase 1 or phase 2, it would include just that feedback path.

You definitely don't want to use acnames/actimes with tran analysis for this (I said that was unlikely to be what you want).

Regards,

Andrew.

Hello Andrew,

That's mean If the probe was just in the loop for phase 1(for example), the pstb analysis will give me the "time-averaged loop gain"  just within this phase 1. Am I right?

Now I just the simulation by inserting the iprobe (now I am just using a single-ended amplifier made of VCCS, resistor. 80 dB DC gain) into the auto-zeroing loop (phi1 in Fig. 1). Then run the PSS+PSTB analysis. The location of the iprobe is shown as a red box in Fig. 3. After I plot the magnitude of the loop gain (in the "Direct Plot Form"), I found that it didn't give me the expected value (80dB) but a gain of  22.26dB. I was wonder what's wrong about ti.

Fig. 3

Best,

shen

What do the clock phases look like (from the PSS time domain results)? Can post a plot?

Note that you're still looking at the time-averaged loop gain over the whole period, not just when that switch is enabled. I'm afraid I don't have enough bandwidth this week to put together a similar example to try it out (I have the day job to do...)

Andrew.

Hello Andrew,

these pictures show my test bench and simulation results:

Schematic : the opamp made of  VCCS (1 mS), resistor (1M Ohm), capacitor (1f P), with gain of 80dB, all the other capacitors are equal to 200f

PSS and PSTB setting

PSS time domain result:

PSTB result

Can you please post the input.scs file?

Andrew.

Hello !

Andrew

This is the input.scs file

simulator lang=spectre
global 0
include "/home/yanrongshen/cdslocallib/artist/ahdlLib/quantity.spectre"
include "models.scs"
parameters a=25m Waz2=6 Waz1=6 Waz=8 Wout=2 Win=16 Wcm=2 Cload=.4p \
    cstable=0.8p Vcm=0.6 T=20n Vin=0m power=1.2 Cs=200f Cf=200f \
    pre=power/2.0

// Library name: ringamp2016
// Cell name: ringamp2nd
// View name: schematic
I13 (net060 net053 net054) nand_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I2 (net055 clk_master net057) nand_gate vlogic_high=1 vlogic_low=0 \
        vtrans=0.5 tdel=10p trise=30p tfall=30p
I3 (clk_master clk_master net060) nor_gate vlogic_high=1 vlogic_low=0 \
        vtrans=0.5 tdel=10p trise=30p tfall=30p
I12 (net055 net055 net494) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I11 (net069 net069 net055) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I10 (net054 net054 net069) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=250p trise=30p tfall=30p
I86 (net053 net053 net475) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I85 (net078 net078 net053) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=10p trise=30p tfall=30p
I9 (net057 net057 net078) nor_gate vlogic_high=1 vlogic_low=0 vtrans=0.5 \
        tdel=50p trise=30p tfall=30p
IPRB0 (net090 net277) iprobe
C16 (net359 net090) capacitor c=200.0f
C18 (net502 AGND) capacitor c=1.000f
C15 (net419 VCM) capacitor c=Cload
C13 (net411 net359) capacitor c=Cs
C14 (net359 net395) capacitor c=Cf
R6 (net502 AGND) resistor r=10M
W21 (VCM net359 Phase2e 0) relay vt1=power/2-1m vt2=power/2+1m ropen=100G \
        rclosed=10.0
W28 (net419 net375 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W24 (net457 net395 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W25 (net395 net502 Phase1 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W27 (net457 net411 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W20 (net502 net419 Phase1 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W23 (net277 net502 Phase2 0) relay vt1=power/2-1m vt2=power/2+1m \
        ropen=100G rclosed=10.0
W22 (net411 VCM Phase1 0) relay vt1=power/2-1m vt2=power/2+1m ropen=100G \
        rclosed=10.0
V3 (VCM AGND) vsource dc=600.0m type=dc
V0 (AGND 0) vsource type=dc
V1 (AVDD AGND) vsource dc=1.2 type=dc
V5 (DVDD 0) vsource type=dc
V15 (net375 0) vsource dc=pre type=dc
V16 (net457 VCM) vsource dc=Vin type=dc
I54 (net470 net486 net465) or_gate vlogic_high=1.2 vlogic_low=0 vtrans=0.6 \
        tdel=20p trise=20p tfall=20p
I53 (net486 net470 Phase2e) and_gate vlogic_high=1.2 vlogic_low=0 \
        vtrans=0.6 tdel=20p trise=20p tfall=20p
I2289 (net469 net470) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I57 (Phase2e inv_Phase2e) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
I2291 (net475 net469) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I2287 (net494 net483) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I58 (Phase2 inv_Phase2) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
I55 (net465 net480) not_gate vlogic_high=power vlogic_low=0 vtrans=power/2 \
        tdel=20p trise=20p tfall=20p
I56 (net480 Phase2) not_gate vlogic_high=power vlogic_low=0 vtrans=power/2 \
        tdel=20p trise=20p tfall=20p
I2292 (net483 Phase1) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=0 trise=20p tfall=20p
I7 (net488 net486) not_gate vlogic_high=power vlogic_low=0 vtrans=power/2 \
        tdel=20p trise=20p tfall=20p
I2293 (net470 net488) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
I2288 (Phase1 inv_Phase1) not_gate vlogic_high=power vlogic_low=0 \
        vtrans=power/2 tdel=20p trise=20p tfall=20p
V4 (clk_master 0) vsource type=pulse val0=0 val1=1 period=T rise=30p \
        fall=30p width=T/2.0
G3 (net502 VCM net090 VCM) vccs gm=1m
simulatorOptions options reltol=1e-4 vabstol=1e-9 iabstol=1e-15 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    dochecklimit=yes checklimitdest=psf 
dcOpCheckLimit checklimit checkallasserts=yes severity=none
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
pss  pss  fund=50M  harms=0  errpreset=moderate  tstab=500n
+    cmin=10a  method=gear2only  tstabmethod=gear2only  maxacfreq=1G
+    annotate=status
pstb pstb start=1 stop=1G dec=100 probe=IPRB0 annotate=status 
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
asserts info what=assert  where=rawfile
saveOptions options save=allpub subcktprobelvl=2
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/nand_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/nor_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/or_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/and_gate/veriloga/veriloga.va"
ahdl_include "/home/yanrongshen/cdslocallib/artist/ahdlLib/not_gate/veriloga/veriloga.va"