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Should I use the PIN or the NET layer for gnd?

dpalomeq

Hi,

I have a layout of a simple PMOS transistor passing DRC, LVS and QRC by using the PIN layer MET1 purpose for the 4 terminals and the connection for the general p-substrate (community.cadence.com/.../37368).

I have some doubts about this because the gnd! connection to the p-substrate is not a PIN in my PMOS cell. How should I implement the p-substrate connection then? Maybe with the NET layer MET1 purpose?

Thanks in advanced!

David.

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  • dpalomeq

    Hi Marc,

    After some checks, I discovered that the right way was treating vdd! and gnd! in the same way than the rest of the pins (even though they are not pins in my schematics). Thus, I have placed labels in the PIN layer with purpose MET1 for all of them.

    Thanks for your help!

    David.

Reply
  • dpalomeq

    Hi Marc,

    After some checks, I discovered that the right way was treating vdd! and gnd! in the same way than the rest of the pins (even though they are not pins in my schematics). Thus, I have placed labels in the PIN layer with purpose MET1 for all of them.

    Thanks for your help!

    David.

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