detecting process corner from within verilogA model

Thank you, I am following this thread because I need to implement the same and I have a question.

I have created a file called "wrapper.scs" which looks exaclty like this:

library wrapper
section NN
parameters corner=1
include "gpdk.scs" section=NN
endsection NN

section FF
parameters corner=2
include "gpdk.scs" section=FF
endsection FF

endlibrary wrapper

In ADE-L I select Setup/Model-Libraries/
then I select the path to the model file "wrapper.scs" and I can select between the two sections "NN" and "FF" (the original file gpdk.scs has more sections). So this part is working fine.

My question is how to read the value of the parameter "corner" into the veriloga model. I am lost here.

Thank you very much!

You can create a parameter in your veriloga model e.g. parameter real getcorner = 1; .  Based on the value of of 'getcorner', you can code the functionality in verilogA model using if/else.

Then when you instantiate the model, you can pass it the value of 'corner' (coming from models) as:

 I0 (x y z) cellA getcorner=corner

ahdl_include "/path/to/cellA.va"

Regards,

Saloni

Hi Saloni,

thank you for your reply.

Implementing the functionality in the verilogA model using the value of the parameter and if/else is clear.

My question is how to pass the value from the "wrapper.scs" to the verilogA model?

This is my file "wrapper.scs":

library wrapper
section NN
parameters corner=1
include "gpdk.scs" section=NN
endsection NN

section FF
parameters corner=2
include "gpdk.scs" section=FF
endsection FF

endlibrary wrapper

This is my model "veriloga.va":

`include "discipline.h"
`include "constants.h"
module inv(A, Y);
input A;
output Y;
electrical A, Y;
parameter real getcorner=1; // how to pass "corner" from "gpdk.scs" to "getcorner" of "veriloga.va" ???

endmodule

When I instantiate the verilogA model (cellview name is "veriloga_read_corner") in the schematic testbench I press Q (properties) and set:

CDF Parameter of view      veriloga_read_corner

getcorner                            corner

But I get following error:

nchelp ncelab CUBSPA
ncelab/CUBSPA =
Assigning a string value to a parameter which is declared to be either
real or integer is illegal.

In summary, what I am missing is how to pass the parameter value "corner" defined in "wrapper.scs" to the parameter "getcorner" inside the "veriloga.va" model.

Thank you very much for your help.

I just tried this on a small testcase and here's what I had to do. When you run netlisting from ADE, do you get a design variable called 'corner' added to the state? You can give the default value to 'corner' in ADE state e.g. 1, and then run the simulation. Spectre will then see variable corner being defined more than once, so depending upon your setup, you might get an error for the same parameter being defined twice. To get past that error, you can set Simulation option redefinedparams=warning. The value coming from models will override the value set in ADE. Hope this helps.

Regards,
Saloni

Thank you again Shaloni.

Indeed I get the following error:

ERROR (SFE-59): ".../models/spectre/wrapper.scs" 9: Parameter `corner' was previously defined.
Please try to add `+spice' in command line or option `redefinedparams' in netlist to avoid these type of errors.

Following your suggestion I do
ADE-L/Simulation/Options/Analog/
Check Tab
redefinedparams [x] warning /Apply/ok

and this is working as expected. I can see how the parameter "getcorner" inside the veriogA model takes the value given by parameter "corner" inside the "wrapper.scs" model file.

Thank you very much for your help! 

Hi Saloni

I followed the same steps as mentioned above 

But in my case the the default value given in the ADE-L is taken as corner. I mean the values coming from the model is not overriding the ADE-L variable.

So what I can do to take the corner values from model file instead of ADE-L?

Thans & Regards,

Shreev

Hi Shreev,

I don't think anything special is needed for the flow to work. Can you set the option redefinedparams=error and share your Spectre log? You should get an error because of the same parameter being redefined.

Regards,

Saloni

HI Saloni,

As per your suggestion I set the option redefineparams = error instead of warning and i get the following error:

Parameter `corner' was previously defined. Please try to add
`+spice' in command line or option `redefinedparams' in netlist to
avoid these type of errors. 

I am still searching for the solution to get override the ADE-L value with Model file values but no solution yet.

Thanks!

Shreev.

Hi Shreev,

Can you paste here the header of your Spectre netlist? I'd like to see the part where the global variables are being defined and model files are called. As an example:

// Generated for: spectre
// Generated on: May 16 16:56:59 2018
// Design library name: testLib
// Design cell name: BUF_sim
// Design view name: config
simulator lang=spectre
global 0
parameters Vsup=1.8 Vgnd=0 Vin=1.8
include "gpdk090.scs" section=NN

Regards,

Saloni

Following on from Saloni's suggestion, if the parameters are after the model files, perhaps you have:

envSetVal("spectre" "netlistModelFileFirst" 'boolean t)

in your environment. Suggest you try calling:

envGetVal("spectre" "netlistModelFileFirst") and seeing if that returns t rather than nil (which is the default).

Regards,

Andrew.

Hi Saloni,

Thanks for your reply.

First of all I would like to mention here that I am using the AMS simulator for this purpose.

If I understood correct I should simulate my Verilog-a code using AMS simulator.

As you can find the AMS netlist as follows: 

// Design library name: wk_BG
// Design cell name: corner_tb
// Design view name: config
// Solver: Spectre

`include "disciplines.vams"
`include "userDisciplines.vams"
// Library - wk_BG, Cell - corner_tb, View - schematic
// LAST TIME SAVED: May 16 17:40:38 2018
// NETLIST TIME: May 16 17:55:54 2018
`timescale 1ns / 1ns

`worklib wk_BG
`view schematic

(* cds_ams_schematic *)

module corner_tb ();

corner #( .getcorner(cds_globals.corner) ) I1 ( .Y(my_corner),
.A(net1));

endmodule
`noworklib
`noview

// END AMS-OSS Netlist

// Verilog-AMS cds_globals module for top-level cell:
// wk_BG/corner_tb.
// Generated by ADE.
// Cadence Design Systems, Inc.

Thanks.

Hi Andrew,

Yes According to your suggestion my environment setup is : envGetVal("spectre" "netlistModelFileFirst") = nil

Which I setup using    envSetVal("spectre" "netlistModelFileFirst" 'boolean nil)

Thanks

Hi Andrew,

Yes According to your suggestion my environment setup is : envGetVal("spectre" "netlistModelFileFirst") = nil

Which I setup using    envSetVal("spectre" "netlistModelFileFirst" 'boolean nil)

Thanks

Although that's not going to be the issue here - it's a shame  you only just mentioned the rather important fact that you're using AMS!

Verilog-A can be simulated with Spectre. Verilog-AMS however requires AMS (you can of course simulate Verilog-A too, but there's no requirement to use AMS for VerilogA).

I'm not sure you can have spectre parameters in model files overriding design variables netlisted into the cds_globals module - they are two different namespaces in the simulator. I'm not aware of a way around this. There might be a way by having the VerilogAMS variable use $cgav (i.e. $cds_get_analog_value) to look up a spectre parameter. I've never tried this - this is just a wild guess based on a quick read of the manual. I'll see if Saloni has some bandwidth to try this (I'm travelling for a few days so definitely don't).

Regards,

Andrew.