detecting process corner from within verilogA model

Thank you again Shaloni.

Indeed I get the following error:

ERROR (SFE-59): ".../models/spectre/wrapper.scs" 9: Parameter `corner' was previously defined.
Please try to add `+spice' in command line or option `redefinedparams' in netlist to avoid these type of errors.

Following your suggestion I do
ADE-L/Simulation/Options/Analog/
Check Tab
redefinedparams [x] warning /Apply/ok

and this is working as expected. I can see how the parameter "getcorner" inside the veriogA model takes the value given by parameter "corner" inside the "wrapper.scs" model file.

Thank you very much for your help! 

Hi Saloni

I followed the same steps as mentioned above 

But in my case the the default value given in the ADE-L is taken as corner. I mean the values coming from the model is not overriding the ADE-L variable.

So what I can do to take the corner values from model file instead of ADE-L?

Thans & Regards,

Shreev

Hi Shreev,

I don't think anything special is needed for the flow to work. Can you set the option redefinedparams=error and share your Spectre log? You should get an error because of the same parameter being redefined.

Regards,

Saloni

HI Saloni,

As per your suggestion I set the option redefineparams = error instead of warning and i get the following error:

Parameter `corner' was previously defined. Please try to add
`+spice' in command line or option `redefinedparams' in netlist to
avoid these type of errors. 

I am still searching for the solution to get override the ADE-L value with Model file values but no solution yet.

Thanks!

Shreev.

Hi Shreev,

Can you paste here the header of your Spectre netlist? I'd like to see the part where the global variables are being defined and model files are called. As an example:

// Generated for: spectre
// Generated on: May 16 16:56:59 2018
// Design library name: testLib
// Design cell name: BUF_sim
// Design view name: config
simulator lang=spectre
global 0
parameters Vsup=1.8 Vgnd=0 Vin=1.8
include "gpdk090.scs" section=NN

Regards,

Saloni

Following on from Saloni's suggestion, if the parameters are after the model files, perhaps you have:

envSetVal("spectre" "netlistModelFileFirst" 'boolean t)

in your environment. Suggest you try calling:

envGetVal("spectre" "netlistModelFileFirst") and seeing if that returns t rather than nil (which is the default).

Regards,

Andrew.

Hi Saloni,

Thanks for your reply.

First of all I would like to mention here that I am using the AMS simulator for this purpose.

If I understood correct I should simulate my Verilog-a code using AMS simulator.

As you can find the AMS netlist as follows: 

// Design library name: wk_BG
// Design cell name: corner_tb
// Design view name: config
// Solver: Spectre

`include "disciplines.vams"
`include "userDisciplines.vams"
// Library - wk_BG, Cell - corner_tb, View - schematic
// LAST TIME SAVED: May 16 17:40:38 2018
// NETLIST TIME: May 16 17:55:54 2018
`timescale 1ns / 1ns

`worklib wk_BG
`view schematic

(* cds_ams_schematic *)

module corner_tb ();

corner #( .getcorner(cds_globals.corner) ) I1 ( .Y(my_corner),
.A(net1));

endmodule
`noworklib
`noview

// END AMS-OSS Netlist

// Verilog-AMS cds_globals module for top-level cell:
// wk_BG/corner_tb.
// Generated by ADE.
// Cadence Design Systems, Inc.

Thanks.

Hi Andrew,

Yes According to your suggestion my environment setup is : envGetVal("spectre" "netlistModelFileFirst") = nil

Which I setup using    envSetVal("spectre" "netlistModelFileFirst" 'boolean nil)

Thanks

Although that's not going to be the issue here - it's a shame  you only just mentioned the rather important fact that you're using AMS!

Verilog-A can be simulated with Spectre. Verilog-AMS however requires AMS (you can of course simulate Verilog-A too, but there's no requirement to use AMS for VerilogA).

I'm not sure you can have spectre parameters in model files overriding design variables netlisted into the cds_globals module - they are two different namespaces in the simulator. I'm not aware of a way around this. There might be a way by having the VerilogAMS variable use $cgav (i.e. $cds_get_analog_value) to look up a spectre parameter. I've never tried this - this is just a wild guess based on a quick read of the manual. I'll see if Saloni has some bandwidth to try this (I'm travelling for a few days so definitely don't).

Regards,

Andrew.

Actually, even with AMS, I get the correct behaviour and the value from device models is used in verilog-A. When Spectre sees the same parameter again in model files, here's the warning saying that the previous definition will be ignored:

    WARNING (SFE-2297):
        "include_corner.scs" 3:
        Parameter `cornerval' is already defined in the same block, previous
        definition is ignored.

How are you verifying whether the value from models is used or not? Can you add a $display in the verilogA model to print the value of 'corner' and check what gets printed in irun.log?