Liberate for library file

Is this a valid arc for this cell?

cell=balloon_sim_nognd, pin=NRESTORE, related_pin=CK, timing_type=removal_rising, when=(!D * !SAVE), rise_constraint

Hi Guangjun,

This is the error  timing arc I have said. I am not sure if it's not valid for the cell.  NRESTORE is low-active and maybe an asynous input pin.  So, I use the write_template to get all the arcs from the incomplete lib file and run agagin with the given arcs, which the above error removal arc is eliminated.

According to the definition, " Removal time for sequential cells is the minimum length of time at which the set or reset signal must remain after the active edge of the clock to ensure correct functioning of the cell. " I don't understant why there are so many arcs.

Regard,

Fengye

Hi Guangjun,

After I set 'NRESTORE' as a Synchronous input, there are still more problems about the arcs. The all arcs generated by Liberate has a possibility of error. If it's true to eliminate some of them.

Regared,

Fengye

Hi Guangjun,

I looked the Liberate manual and find some commands like

"read_library TSMC_balloon_ss_0p99v_125c_ecsm.lib
# set timing check variables
set vital_timing_violation_format "Tviol_edge"
set vital_recrem_violation_format "Rviol_ref_edge"
set vital_timing_info_format "Tinfo_ref_edge"
set vital_recrem_info_format "Rinfo_ref_edge"
# Output a Vital file
write_vital TSMC_balloon_ss_0p99v_125c_ecsm.vhd"

The the vhd file has some reminder about error, you know how this can help me deal this problem.

Thanks a lot!

Regards,

Fengye

Hi Fengue,

You can not simply ignore a failed arc characterisation. 'removal' constraint is like 'hold'. You should ask the designer to clarify whether this arc is valid. If it is, you can save the failed deck and do debug. there are suggestions in the logfile, which should be tried first. You can also save the passsed deck and use them for debug reference.

For the function, you may have to add it yourself, as this cell may not be normal "standard", but a custom digital. the right function can only be provided by the cell designer and the STA digital engineer. You can also use a similar cell as a reference.

Guangjun 

Is this the same library? If so, it is meant to fail, as your library is not complete.

If 'NRESTORE' is NOT Synchronous, then you can not define it as Synchronous.

one quick question: does this cell pass characterisation on other corners, eg. TT?

Hi Guangjun,

Thanks for your reply! 'NRESTORE' may be asynchronous.  The error removal arc may be eliminated. Then the lib can be gennated without error, but still with warnning about "write_verilog". This same case can happer at SS,TT FF cornner. 

When the lib without above removal arc is used for synthesis, some warnning shows the balloon cell is unusable. This is the reason I want to analyze the correctness of the lib file.

After you tried that, are the complete lib file generated?

Regard,

Fengye 

Hi Fengye,

I saw the failed arc, but did not try to debug it. It can be very time consuming and may need knowledge about the logic behavior of the cell. In any case, you need to find out if this arc is valid.

It is not clear to me that the "unusable" warning is due to the removed "removal". What synthesis/tool are you talking about? can you get help on why this warning is issued? in general, a missing arc does not always cause problem. 

regards,

Guangjun