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Liberate : generate lib file for a level shift cell

fengye

Hi,

    Did anyone generate the lib file for a level shift with liberate? I don't know how to make some settings.

(1) For the following netlist, 

.SUBCKT ls_cell IN OUT VDDH VDDL VSS
*.PININFO IN:I OUT:O VDDH:B VDDL:B VSS:B
MPM0 A net10 VDDH VDDH P_12_LLRVT W=100e-9 L=200n M=1
MPM1 net10 net10 VDDH VDDH P_12_LLRVT W=100e-9 L=60n M=1
MPM12 net069 net50 VDDH VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM11 net058 net50 net069 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM8 net071 OUT net046 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM7 net50 OUT net071 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM6 net046 OUT net072 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM10 OUT net50 net070 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM5 B A net10 VDDH P_12_LLHVT W=100e-9 L=60n M=1
MPM4 net072 OUT VDDH VDDH P_12_LLHVT W=100e-9 L=500n M=1
MPM9 net070 net50 net058 VDDH P_12_LLHVT W=100e-9 L=500n M=1
MNM6 A In_not VSS VSS N_12_LLLVT W=2e-6 L=60n M=1
MNM8 net50 A VSS VSS N_12_LLLVT W=150e-9 L=100n M=1
MNM7 OUT B VSS VSS N_12_LLLVT W=150e-9 L=100n M=1
MNM3 In_not IN VSS VSS N_12_LLLVT W=2e-6 L=60n M=1
MNM5 B IN VSS VSS N_12_LLLVT W=2e-6 L=60n M=1
MPM3 In_not IN VDDL VDDL P_12_LLLVT W=4e-6 L=60n M=1
.ENDS

(2) the template is 


define_template -type delay \
-index_1 {0.008 0.28 } \
-index_2 {0.01 0.3 } \
delay_template_2x2

define_template -type power \
-index_1 {0.008 0.28 } \
-index_2 {0.01 0.3 } \
power_template_2x2


define_cell \
-input { IN } \
-output { OUT } \
-pinlist { IN OUT } \
-delay delay_template_2x2 \
-power power_template_2x2 \
ls_cell

define_leakage -when "IN" ls_cell
define_leakage -when "!IN" ls_cell

# delay arcs from IN => OUT positive_unate combinational
define_arc \
-vector {XX} \
-related_pin IN \
-pin OUT \
ls_cell

# delay arcs from IN => Y positive_unate combinational
define_arc \
-vector {FF} \
-related_pin IN \
-pin OUT \
ls_cell

(3) the multi-voltage 

set VDD_VALUE 1.20
set VDDS_VALUE 0.30

set_vdd VDDH ${VDD_VALUE}
set_vdd VDDL ${VDDS_VALUE}

(4) the error reminding

ERROR (LIB-88): (define_arc): Ignoring arc for cell: 'ls_cell', pin: 'OUT' X, related_pin: 'IN' X, vector: 'XX', pinlist: 'IN OUT' because of one or more invalid values (for example: value 'X' for signal 'OUT'). The valid values for the pin and related_pin are 'R' and 'F'. All other signals can use: '0', '1', 'R', 'F' or 'X'. Correct the Tcl and rerun.

(5) the input_volttage_range, output_voltage_range，how to get these, I need to use userdate to add these attribute.

I hope someone can help me .

Thanks a lot!

Parents
  • Guangjun Cao
    in reply to Guangjun Cao

    define_arc \
    -vector {XX} \  ==>change to RR
    -related_pin IN \
    -pin OUT \
    ls_cell

  • fengye
    in reply to Guangjun Cao

    Hi, Guangjun,
    Thanks for your reply! I change the define_arc and use the following setting "
    set VDD_VALUE 1.20
    set VDDS_VALUE 0.60
    set_vdd VDDH ${VDD_VALUE}
    set_vdd VDDL ${VDDS_VALUE}

    set_pin_vdd -supply_name VDDH ls_cell OUT ${VDD_VALUE}
    set_pin_vdd -supply_name VDDL ls_cell IN ${VDDS_VALUE}
    set_var voltage_map 2
    "

    The error reminder are as follows:

    ERROR (LIB-809): (define_arc): No vector was found for the arc of cell:'ls_cell', r_pin:'IN' r, pin:'OUT' r. This arc in the resulting library may not be correct. Update the 'define_arc' command and rerun.
    Performance statistics for ls_cell: Spectre cpu time = 26.0 seconds, total cpu time = 26.0 seconds, wall clock time = 50.0 seconds.
    ERROR (LIB-55): No valid vectors were found for the user provided define_arc for arc of cell:'ls_cell', r_pin:'IN', r_pin dir:'r', pin:'OUT', pin dir:'r', type:'combinational rise_transition', vector:'RR'. To debug, review the saved simulation results for deck: delay_1. Review port direction and vector values. Review spice deck(s) for valid delay measurements.

    Regards,

    fengye

  • Guangjun Cao
    in reply to fengye

    please use the saved deck to debug. check if the voltage levels are all correct.

  • fengye
    in reply to Guangjun Cao

    Hi,guangjun

     I check the file, and  I find "X1 IN OUT VSS VDDL VDDH ls_cell
    VVDDH VDDH 0 1.2
    VVDDL VDDL 0 0.6
    VVSS VSS 0 0" in the sim.sp . That means the voltage level is correct.

    For the error "ERROR (LIB-809): (define_arc): No vector was found for the arc of cell:'ls_cell', r_pin:'IN' r, pin:'OUT' r. This arc in the resulting library may not be correct. Update the 'define_arc' command and rerun.
    Performance statistics for ls_cell: Spectre cpu time = 26.0 seconds, total cpu time = 26.0 seconds, wall clock time = 50.0 seconds.
    ERROR (LIB-55): No valid vectors were found for the user provided define_arc for arc of cell:'ls_cell', r_pin:'IN', r_pin dir:'r', pin:'OUT', pin dir:'r', type:'combinational rise_transition', vector:'RR'. To debug, review the saved simulation results for deck: delay_1. Review port direction and vector values. Review spice deck(s) for valid delay measurements.
    "

    If I remove the define_arc for “RR”， there ia no error. So, this is because the error arc template?

    Besides, the attribute of "input/output voltage range" doesn't occur, this is needed to be added by using the userdate?

    Regards,

    fengye

Reply
  • fengye
    in reply to Guangjun Cao

    Hi,guangjun

     I check the file, and  I find "X1 IN OUT VSS VDDL VDDH ls_cell
    VVDDH VDDH 0 1.2
    VVDDL VDDL 0 0.6
    VVSS VSS 0 0" in the sim.sp . That means the voltage level is correct.

    For the error "ERROR (LIB-809): (define_arc): No vector was found for the arc of cell:'ls_cell', r_pin:'IN' r, pin:'OUT' r. This arc in the resulting library may not be correct. Update the 'define_arc' command and rerun.
    Performance statistics for ls_cell: Spectre cpu time = 26.0 seconds, total cpu time = 26.0 seconds, wall clock time = 50.0 seconds.
    ERROR (LIB-55): No valid vectors were found for the user provided define_arc for arc of cell:'ls_cell', r_pin:'IN', r_pin dir:'r', pin:'OUT', pin dir:'r', type:'combinational rise_transition', vector:'RR'. To debug, review the saved simulation results for deck: delay_1. Review port direction and vector values. Review spice deck(s) for valid delay measurements.
    "

    If I remove the define_arc for “RR”， there ia no error. So, this is because the error arc template?

    Besides, the attribute of "input/output voltage range" doesn't occur, this is needed to be added by using the userdate?

    Regards,

    fengye

Children
  • Guangjun Cao
    in reply to fengye

    1. please read the article with the link I sent you. you need to define "input_signal_level" attribute for level shifter.

    2. please do spice simulation, and check the waveform/level.

  • fengye
    in reply to Guangjun Cao

    I read the article you send me  and I use the following setting from the article reference

    set_vdd -cells ls_cell -attribute (std_cell_main_rail true) VDDL 0.6
    set_vdd -cells ls_cell -attribute (related_bias_pin vdds direction inout} VDDL 0.6
    set_pin_vdd -leakage_add_to_supply VDDL -supply_name VDDL ls_cell A 0.6
    set_pin_vdd -supply_name VDDH ls_cell Y 1.2
    set_attribute -cells ls_cell -pins {A} input_signal_level VDDL
    set_attribute -cells ls_cell -pins {A} related_power_pin VDDL

    The error occurs agiain!

    *Warning* (set_gnd) : Gnd supply VSS has already been set, overriding previous value to 0
    bad value "VDDL" for parameter
    voltage float () Voltage value
    while executing
    "OptDoOne descriptions state arguments"
    (procedure "OptDoAll" line 30)
    invoked from within
    "OptDoAll desc arglist"
    (procedure "::tcl::OptKeyParse" line 10)
    invoked from within
    "::tcl::OptKeyParse set_vdd $args"
    (procedure "set_vdd" line 1)
    invoked from within
    "set_vdd -cells ls_cell -attribute (std_cell_main_rail true) VDDL 0.6"

    I will simulate the spice according to your suggestion.

    Thanks again!

    Regards,

    fengye

  • Guangjun Cao
    in reply to fengye

    these two lines have syntax error,

    set_vdd -cells ls_cell -attribute (std_cell_main_rail true) VDDL 0.6
    set_vdd -cells ls_cell -attribute (related_bias_pin vdds direction inout} VDDL 0.6

    please use {} .

  • fengye
    in reply to Guangjun Cao

    Hi, guangjun,

     Thanks for your reply! After I make simulation with your suggestion, for the error arc, 'ls_cell', r_pin:'IN' r, pin:'OUT' r., the out cannot rise to the voltage VDDH. So, the measurement is failed. Maybe the circuit have error.

    When I change the new level shifter netlist, there is no error. But in the output lib file, there is no input/output voltage range for the input/output pin. Can you tell the voltagerange should be added by userdate or by some other liberate commands settings?

    Regards,

    fengye

  • Guangjun Cao
    in reply to fengye

    Hi Fengye,

    1. please show me the attribute of input/output voltage range in your reference library.

    2.please show me your command for defining these attribute. also, check the logfile to see if the attributes are failed to be applied.

    Regards,

    guangjun

  • fengye
    in reply to Guangjun Cao

    Hi,Guangjun,

    1. In my reference library, the attribute are "      input_voltage_range (0.8, 1.4);" and "      output_voltage_range (0.8, 1.4);"

    2. I don't define these attribute ,and I just define the VDDL and VDDH in the char.tcl. I guess these attribution should be added by userdata. 

    Regards,

    fengye

  • Guangjun Cao
    in reply to fengye

    Hi Fengye,

    you can certainly put the input_voltage_range in the user data file. set_attribute command is an alternative way. In this case, there might be a syntax issue--you have to give it a try. if set_attribute -cell ls_cell -pin {add_pin_name_here} input_voltage_range (0.8, 1.4) does not work, try "(0.8, 1.4)" or "\(0.8, 1.4\)" or \(0.8, 1.4\).

    Guangjun

  • fengye
    in reply to Guangjun Cao

    Hi Guangjun,

        Thanks for your reply! With your help, I have solved my problem. It's so kind of you. 

        Regards,

    fengye 

  • Guangjun Cao
    in reply to fengye

    I am very glad to hear that!

    Guangjun

  • fengye
    in reply to Guangjun Cao

    Hi, Guangjun 

        Recently, I find another question about the characterization of  level shifter. There is no leakage value in the generated lib file.  In the template,  I use "define_leakage -when "IN" ls_cell
    define_leakage -when "!IN" ls_cell" . Besides, in the char.tcl, "set_pin_vdd -leakage_add_to_supply VDDL -supply_name VDDL ls_cell IN ${VDDS_VALUE}" is added. 

    But, in the lib file, it exhibits "    cell_leakage_power : 0;" and there isn't any leakage power calculation in the record file. Then I simulate the netlist with hspice, and the cell has leakage power. Did you meet this question?

       Regards!

      fengye

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