Liberate : generate lib file for a level shift cell

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V0000091BSOUA2&pageName=ArticleContent

I found this article in our database.

define_arc \
-vector {XX} \  ==>change to RR
-related_pin IN \
-pin OUT \
ls_cell

1. please read the article with the link I sent you. you need to define "input_signal_level" attribute for level shifter.

2. please do spice simulation, and check the waveform/level.

I read the article you send me  and I use the following setting from the article reference

set_vdd -cells ls_cell -attribute (std_cell_main_rail true) VDDL 0.6
set_vdd -cells ls_cell -attribute (related_bias_pin vdds direction inout} VDDL 0.6
set_pin_vdd -leakage_add_to_supply VDDL -supply_name VDDL ls_cell A 0.6
set_pin_vdd -supply_name VDDH ls_cell Y 1.2
set_attribute -cells ls_cell -pins {A} input_signal_level VDDL
set_attribute -cells ls_cell -pins {A} related_power_pin VDDL

The error occurs agiain!

*Warning* (set_gnd) : Gnd supply VSS has already been set, overriding previous value to 0
bad value "VDDL" for parameter
voltage float () Voltage value
while executing
"OptDoOne descriptions state arguments"
(procedure "OptDoAll" line 30)
invoked from within
"OptDoAll desc arglist"
(procedure "::tcl::OptKeyParse" line 10)
invoked from within
"::tcl::OptKeyParse set_vdd $args"
(procedure "set_vdd" line 1)
invoked from within
"set_vdd -cells ls_cell -attribute (std_cell_main_rail true) VDDL 0.6"

I will simulate the spice according to your suggestion.

Thanks again!

Regards,

fengye

these two lines have syntax error,

set_vdd -cells ls_cell -attribute (std_cell_main_rail true) VDDL 0.6
set_vdd -cells ls_cell -attribute (related_bias_pin vdds direction inout} VDDL 0.6

please use {} .

Hi, guangjun,

 Thanks for your reply! After I make simulation with your suggestion, for the error arc, 'ls_cell', r_pin:'IN' r, pin:'OUT' r., the out cannot rise to the voltage VDDH. So, the measurement is failed. Maybe the circuit have error.

When I change the new level shifter netlist, there is no error. But in the output lib file, there is no input/output voltage range for the input/output pin. Can you tell the voltagerange should be added by userdate or by some other liberate commands settings?

Regards,

fengye

Hi Fengye,

1. please show me the attribute of input/output voltage range in your reference library.

2.please show me your command for defining these attribute. also, check the logfile to see if the attributes are failed to be applied.

Regards,

guangjun

Hi,Guangjun,

1. In my reference library, the attribute are "      input_voltage_range (0.8, 1.4);" and "      output_voltage_range (0.8, 1.4);"

2. I don't define these attribute ,and I just define the VDDL and VDDH in the char.tcl. I guess these attribution should be added by userdata. 

Regards,

fengye

Hi Fengye,

you can certainly put the input_voltage_range in the user data file. set_attribute command is an alternative way. In this case, there might be a syntax issue--you have to give it a try. if set_attribute -cell ls_cell -pin {add_pin_name_here} input_voltage_range (0.8, 1.4) does not work, try "(0.8, 1.4)" or "\(0.8, 1.4\)" or \(0.8, 1.4\).

Guangjun

Hi Guangjun,

    Thanks for your reply! With your help, I have solved my problem. It's so kind of you. 

    Regards,

fengye 

I am very glad to hear that!

Guangjun

Hi, Guangjun 

    Recently, I find another question about the characterization of  level shifter. There is no leakage value in the generated lib file.  In the template,  I use "define_leakage -when "IN" ls_cell
define_leakage -when "!IN" ls_cell" . Besides, in the char.tcl, "set_pin_vdd -leakage_add_to_supply VDDL -supply_name VDDL ls_cell IN ${VDDS_VALUE}" is added. 

But, in the lib file, it exhibits "    cell_leakage_power : 0;" and there isn't any leakage power calculation in the record file. Then I simulate the netlist with hspice, and the cell has leakage power. Did you meet this question?

   Regards!

  fengye

Hi, Guangjun 

    Recently, I find another question about the characterization of  level shifter. There is no leakage value in the generated lib file.  In the template,  I use "define_leakage -when "IN" ls_cell
define_leakage -when "!IN" ls_cell" . Besides, in the char.tcl, "set_pin_vdd -leakage_add_to_supply VDDL -supply_name VDDL ls_cell IN ${VDDS_VALUE}" is added. 

But, in the lib file, it exhibits "    cell_leakage_power : 0;" and there isn't any leakage power calculation in the record file. Then I simulate the netlist with hspice, and the cell has leakage power. Did you meet this question?

   Regards!

  fengye

Fengye,

I am on vacation now, so won't be able to answer your questions timely.

You can try char_library -trial, without other options. Hopefully liberate can generate a linbrary with leakage arcs. Then, you can use read_library to read in this library and then write_template -verbose to generate a template. This template file should have define_leakage command.

Generally, define_leakage commands have when conditions with both input and output, eg. For a cell with function as out=in, you will see two arcs with -when in * out, and -when !Out * !In.

Hope this helps,

Guangjun

Hi, Guangjun,

    Thanks for your suggestion! I get the "define_leakage" for the level shifter.，

define_leakage -when "IN*OUT" ls_cell
define_leakage -when "!IN*!OUT" ls_cell

or

define_leakage -when "IN" ls_cell
define_leakage -when "!IN" ls_cell

 However, there still isn't leakage information. For one anther level shifter, the same setting can get leakage value. For my used level shifter, I make the dc simulation, and can get the leakage value, but it cannot get from the liberate. I guess the commands for "define_leakage" is correct, but still don't know the reason.

 I will try again! Hope you have a good time on your vocation!

 Regards,

fengye