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Generating .lib file for synthesis using Genus from transistor level cells using Virtuoso

iamKarthikBK

I am trying to create a standard cell library by drawing the transistor level schematics in Virtuoso.

I want to be able to use these cells for synthesis using Genus.

I understand that Genus requires a .lib file to be able to perform the synthesis (is there any other file that's required?)

I have read that I'll have to use Liberate to generate the .lib file and Liberate actually needs a spectre/spice netlist of each of the cells that are being drawn.

My progress till now:

1) Draw the schematics of all the cells that I want to include in the library

2) Generate the symbol view for each of these cells

3) Draw the layouts for each of these cells

I tried going into ADE L and Simulation->Netlist->Create as per the documentation I read using my COS account, this gives me a spectre netlist. But when I try to save this netlist to the spectre view created using Create->Cellview from Cellview it says there were errors parsing the spectre file, but the errors/warnings don't show up. An empty error window opens up.

Can someone point me to any relevant documentation? I want to be able to synthesize designs with Genus using cells I define in the transistor level using Virtuoso.

I am using IC618 GENUS191 LIBERATE192 (The versions correct to the best of my memory) on a Red Hat Enterprise Linux 6 distribution with the distro kernel (2.x)

Thank you so much in advance for your time!

  • in reply to iamKarthikBK

    I'm not sure why the nets have been named with a "global" suffix (the explanation mark) when the schematic has non-global names. I don't have access to that PDK (which is why this should go through customer support; then an AE who has time to explore this can take a look). I suspect that the Quantus error is that. you should probably be specifying the reference node as "gnd"; given that you've not shown your Quantus setup, it's hard to know for certain.

    Usually for academic institutions you can either (if part of the Europractice scheme) contact Europractice support, or for Universities elsewhere your university contact (usually the professor who looks after the scheme) can log support questions on your behalf. Individual students only get the reference key access so that you can search issues, look at solutions, and access other material, but you can't create support cases directly (it needs to go through the filter of the coordinator at your university first to ensure that questions that can be handled locally first, can be).

    Andrew

  • in reply to iamKarthikBK

    This issue was resolved! The reference net had to be set as 'gnd' instead of gnd!
    It was my fault in the configuration!


    Thank you so much!

  • in reply to Andrew Beckett

    Yes the reference node was gnd! instead of gnd. Thank you so much! this got resolved!

    Yes we have access to UMC's FDK through the Europractice Consoritum. I will ask my co-ordinator to file a case with Cadence SUpport. Thank you once again :)

  • in reply to iamKarthikBK

    Hello Karthik,

    Were you able to use the created standard cell library(.lib) in the Genus to synthesize the design?

  • in reply to Ponde Manoj Kumar

    I still haven't been able to generate the .lib file
    Here's the latest update : community.cadence.com/.../1375478

    thanks

  • in reply to iamKarthikBK

    I was able to generate the .lib file successfully by following this  run_char.tgz  downloaded from the link
    https://support.cadence.com/apex/articleattachmentportal?id=a1O0V000007MgZLUA0&pageName=ArticleContent&attachId=0690V000003xCZjQAM&sq=null&caseSessionKey=null
    and just modify the 
    char.tcl
    template.tcl
    cells.tcl
    userdata.lib accordingly.
    And put your generated netlist file in the 'netlist' folder.
    Place your spectre model files inside the 'models' folder.
    I hope this helps.


  • in reply to iamKarthikBK
    Ponde Manoj Kumar said:
    userdata.lib accordingly.

    Hi, Sorry I don't exactly know how to generate this file for my cells. I am assuming this has something to do with the layout, can you please tell me how I can generate this file for the selected cells?

    I read this https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/41157/importing-standard-cell-area-into-lib-file-automatically and they say you need to generate the liberty file first.

    I was able to generate the LEF file from Virtuoso (using av_extracted as the cell view). How do I go about telling liberate about the area of my cells?

    Thanks

  • in reply to iamKarthikBK

    user_data flow is generally used in re-characterization flow. In such a case, a user_data file can be created from the reference library using read_library-->write_userate_library. a user_data file created this way has the same syntax as a regular .lib file, however, there is no data groups in the user_data file but only attributes. The user_data fiel can be used in write_library coomand, which append or replace the attributes. You can certainly manually create a user_data file. You can also user set_attribute commands (before write_library command) to added attributes. The pdf reference manual has details on this command.  

  • in reply to Guangjun Cao

    Hi

    Guangjun Cao said:
    user_data flow is generally used in re-characterization flow.

    Oh, okay.

    Guangjun Cao said:
    The pdf reference manual has details on this command.  

    Okay I'll take a look at that!

    Meanwhile, my characterization flow halts here (it's been like this for over an hour now)

    *Info* : Initializing SKI environment...
    Initializing Spice
    *Info* Adding 10 global models to Spice.
    Building library database
    Processing cell: AND2X1
    (May 22 13:17:16) Finish building module.
    *Info* (char_library) : Cell AND2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/AND2X1.sp
    Processing cell: INVX1
    (May 22 13:17:17) Finish building module.
    *Info* (char_library) : Cell INVX1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/INVX1.sp
    Processing cell: NAND2X1
    (May 22 13:17:17) Finish building module.
    *Info* (char_library) : Cell NAND2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/NAND2X1.sp
    Processing cell: NOR2X1
    (May 22 13:17:17) Finish building module.
    *Info* (char_library) : Cell NOR2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/NOR2X1.sp
    Processing cell: OR2X1
    (May 22 13:17:17) Finish building module.
    *Info* (char_library) : Cell OR2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/OR2X1.sp
    *Info* (char_library) : Cell AND2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/AND2X1.sp
    *Info* (char_library) : Cell INVX1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/INVX1.sp
    *Info* (char_library) : Cell NAND2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/NAND2X1.sp
    *Info* (char_library) : Cell NOR2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/NOR2X1.sp
    *Info* (char_library) : Cell OR2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/OR2X1.sp
    MEM=455 MB
    MEM=455 MB
    (May 22 13:17:17) Generating vectors: AND2X1
    (May 22 13:17:17) Generating vectors: INVX1
    (May 22 13:17:17) Generating vectors: NAND2X1
    (May 22 13:17:17) Generating vectors: NOR2X1
    (May 22 13:17:17) Generating vectors: OR2X1
    MEM=456 MB
    (May 22 13:17:17) Begin of pre-driver matching trans.
    Generating CCST predriver for 2 unique input transition times ..
    (May 22 13:17:17) End of pre-driver matching trans.

    May 22 13:17:17 Thread 3: Cell=OR2X1 (16%) Pin=y Related=a combinational rise_transition
    May 22 13:17:17 Thread 2: Cell=OR2X1 (33%) Pin=y Related=b combinational rise_transition
    May 22 13:17:17 Thread 0: Cell=OR2X1 (50%) Pin=y Related=a combinational fall_transition
    May 22 13:17:37 Thread 1: Cell=OR2X1 (66%) Pin=y Related=b combinational fall_transition

    Can you think of something that could be wrong? I can share the .tcl files here if necessary, but they were taken from here

    Ponde Manoj Kumar said:
    I was able to generate the .lib file successfully by following this  run_char.tgz  downloaded from the link
    https://support.cadence.com/apex/articleattachmentportal?id=a1O0V000007MgZLUA0&pageName=ArticleContent&attachId=0690V000003xCZjQAM&sq=null&caseSessionKey=null

    thanks once again

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