Generating .lib file for synthesis using Genus from transistor level cells using Virtuoso

To do liberate characterization, you need post-layout netlist for each cell that need to be characterized. for this, you do not need a spectre view.

I see. Would you please elaborate a little bit as to how to generate a post layout netlist?

Here are screenshots if in case the net names are confusing :)

I haven't named the nets as 'gnd!' but only as 'gnd'. Same with 'vdd' being named as 'vdd!'. Andrew Beckett Guangjun Cao can you please tell me as to why that happens? 
What does /S_mustGroup_0/vdd! and /D_mustGroup_1/gnd! mean?

I am using UMC's 180nm FDK
Thank you so much for your time and patience in advance, I sincerely appreciate it!

I'm not sure why the nets have been named with a "global" suffix (the explanation mark) when the schematic has non-global names. I don't have access to that PDK (which is why this should go through customer support; then an AE who has time to explore this can take a look). I suspect that the Quantus error is that. you should probably be specifying the reference node as "gnd"; given that you've not shown your Quantus setup, it's hard to know for certain.

Usually for academic institutions you can either (if part of the Europractice scheme) contact Europractice support, or for Universities elsewhere your university contact (usually the professor who looks after the scheme) can log support questions on your behalf. Individual students only get the reference key access so that you can search issues, look at solutions, and access other material, but you can't create support cases directly (it needs to go through the filter of the coordinator at your university first to ensure that questions that can be handled locally first, can be).

Andrew

This issue was resolved! The reference net had to be set as 'gnd' instead of gnd!
It was my fault in the configuration!


Thank you so much!

Yes the reference node was gnd! instead of gnd. Thank you so much! this got resolved!

Yes we have access to UMC's FDK through the Europractice Consoritum. I will ask my co-ordinator to file a case with Cadence SUpport. Thank you once again :)

Hello Karthik,

Were you able to use the created standard cell library(.lib) in the Genus to synthesize the design?

I still haven't been able to generate the .lib file
Here's the latest update : community.cadence.com/.../1375478

thanks

I was able to generate the .lib file successfully by following this  run_char.tgz  downloaded from the link
https://support.cadence.com/apex/articleattachmentportal?id=a1O0V000007MgZLUA0&pageName=ArticleContent&attachId=0690V000003xCZjQAM&sq=null&caseSessionKey=null
and just modify the 
char.tcl
template.tcl
cells.tcl
userdata.lib accordingly.
And put your generated netlist file in the 'netlist' folder.
Place your spectre model files inside the 'models' folder.
I hope this helps.

Ponde Manoj Kumar said:

I hope this helps.

Thanks, I'll try this one out.

Ponde Manoj Kumar said:

userdata.lib accordingly.

Hi, Sorry I don't exactly know how to generate this file for my cells. I am assuming this has something to do with the layout, can you please tell me how I can generate this file for the selected cells?

I read this https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/41157/importing-standard-cell-area-into-lib-file-automatically and they say you need to generate the liberty file first.

I was able to generate the LEF file from Virtuoso (using av_extracted as the cell view). How do I go about telling liberate about the area of my cells?

Thanks

Ponde Manoj Kumar said:

userdata.lib accordingly.

Hi, Sorry I don't exactly know how to generate this file for my cells. I am assuming this has something to do with the layout, can you please tell me how I can generate this file for the selected cells?

I read this https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/41157/importing-standard-cell-area-into-lib-file-automatically and they say you need to generate the liberty file first.

I was able to generate the LEF file from Virtuoso (using av_extracted as the cell view). How do I go about telling liberate about the area of my cells?

Thanks

user_data flow is generally used in re-characterization flow. In such a case, a user_data file can be created from the reference library using read_library-->write_userate_library. a user_data file created this way has the same syntax as a regular .lib file, however, there is no data groups in the user_data file but only attributes. The user_data fiel can be used in write_library coomand, which append or replace the attributes. You can certainly manually create a user_data file. You can also user set_attribute commands (before write_library command) to added attributes. The pdf reference manual has details on this command.  

Hi

Guangjun Cao said:

user_data flow is generally used in re-characterization flow.

Oh, okay.

Guangjun Cao said:

The pdf reference manual has details on this command.  

Okay I'll take a look at that!

Meanwhile, my characterization flow halts here (it's been like this for over an hour now)

*Info* : Initializing SKI environment...
Initializing Spice
*Info* Adding 10 global models to Spice.
Building library database
Processing cell: AND2X1
(May 22 13:17:16) Finish building module.
*Info* (char_library) : Cell AND2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/AND2X1.sp
Processing cell: INVX1
(May 22 13:17:17) Finish building module.
*Info* (char_library) : Cell INVX1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/INVX1.sp
Processing cell: NAND2X1
(May 22 13:17:17) Finish building module.
*Info* (char_library) : Cell NAND2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/NAND2X1.sp
Processing cell: NOR2X1
(May 22 13:17:17) Finish building module.
*Info* (char_library) : Cell NOR2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/NOR2X1.sp
Processing cell: OR2X1
(May 22 13:17:17) Finish building module.
*Info* (char_library) : Cell OR2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/OR2X1.sp
*Info* (char_library) : Cell AND2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/AND2X1.sp
*Info* (char_library) : Cell INVX1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/INVX1.sp
*Info* (char_library) : Cell NAND2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/NAND2X1.sp
*Info* (char_library) : Cell NOR2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/NOR2X1.sp
*Info* (char_library) : Cell OR2X1 found in file /home/TSMC/Desktop/UMC180/Designkits/Cadence_6.1/lowpower/liberate/run_char/netlist/OR2X1.sp
MEM=455 MB
MEM=455 MB
(May 22 13:17:17) Generating vectors: AND2X1
(May 22 13:17:17) Generating vectors: INVX1
(May 22 13:17:17) Generating vectors: NAND2X1
(May 22 13:17:17) Generating vectors: NOR2X1
(May 22 13:17:17) Generating vectors: OR2X1
MEM=456 MB
(May 22 13:17:17) Begin of pre-driver matching trans.
Generating CCST predriver for 2 unique input transition times ..
(May 22 13:17:17) End of pre-driver matching trans.

May 22 13:17:17 Thread 3: Cell=OR2X1 (16%) Pin=y Related=a combinational rise_transition
May 22 13:17:17 Thread 2: Cell=OR2X1 (33%) Pin=y Related=b combinational rise_transition
May 22 13:17:17 Thread 0: Cell=OR2X1 (50%) Pin=y Related=a combinational fall_transition
May 22 13:17:37 Thread 1: Cell=OR2X1 (66%) Pin=y Related=b combinational fall_transition

Can you think of something that could be wrong? I can share the .tcl files here if necessary, but they were taken from here

Ponde Manoj Kumar said:

I was able to generate the .lib file successfully by following this  run_char.tgz  downloaded from the link
https://support.cadence.com/apex/articleattachmentportal?id=a1O0V000007MgZLUA0&pageName=ArticleContent&attachId=0690V000003xCZjQAM&sq=null&caseSessionKey=null

thanks once again

check the sim.lis files in your tmpdir/altos*. if this is not local, use set_var tmpdir <full_path> define it.

you may need to diasble ski (set_var ski_enable 0) and use char_library -extsim spectre 

The following solved the issue

set_var ski_enable 0

set_var extsim_exclusive 1
set_var sim_estimate_duration 0
set_var sim_duration 10

But I think the delay values are incorrectly large. But that should be due to my index values which are probably wrong.

Here's the datasheet: gist.githubusercontent.com/.../datasheet.txt

This issue has been resolved!

Thank you so much!

iamKarthikBK said:

set_var extsim_exclusive 1

The default is 1. and you were using -extsim spectre already. I do not believe this makes any impact, if you are still using what you have described before..

iamKarthikBK said:

set_var ski_enable 0

This is only supposed to be used as debug option. If this solves the issue, then there might be a tool issue, which is very rare. one reason to use this for debug is it creates a deck with model included, which makes the standalone debug simulation easier. 

iamKarthikBK said:

set_var sim_estimate_duration 0

I have told you clearly before that this should not be used as normal characterization. It may lead to unrealistically high power number, in some cases. Using it for debug only, and find the root cause for the failed characterization.

iamKarthikBK said:

set_var sim_duration 10

This again is clearly unrealistically high. the root cause may be your netlist, or how your cell behaves, which needs to looked into.

All the power numbers are zero in the datasheet. if you have not defined power templates or skipped power characterization, this is certainly wrong. 

In terms of long timing and index table, as I have suggested, you can define_min/max_transion and min_output_cap variables (check pdf doc). you simple define the size of index 1/2, eg , you need to define size. one of the install/example has such a template. then, use char_library -auto_index. the tool will create all slew/load table for you to satisfy you defined max_transition.

Just because you have a .lib generated, it does not mean your characterization is good or successful, or the issue is solved. You need to follow my suggestions to go through standard debug process. otherwise, you just keep on getting new issues. this will not go any where. This may also be the reason that a simple characterization has been made so complicated.

Guangjun Cao said:

if you have not defined power templates or skipped power characterization, this is certainly wrong.

I have defined all power, delay, and constraint templates. But the index values (that I calculated might be wrong).

I calculated the the 3 values for index_1 as the "(riseTime + fallTime) / 2" for 1, 4 and 20 inverter loads.

they turned out to be 61.75 ns, 158.9 ns, 794.1 ns respectively.

I calculated the index_2 values as input capacitances for 1, 4, and 16 inverter loads.

18.732 pF, 37.464 pF, 74.928 pF respectively.

These are exactly what I used as index_1 and index_2.

hence, index_1 = { 61.75 158.9 794.1 }

and index_2 = {18.732 37.464 74.928 }

I have used these values for all three (delay, power, constraint) templates.

Guangjun Cao said:

In terms of long timing and index table, as I have suggested, you can define_min/max_transion and min_output_cap variables (check pdf doc). you simple define the size of index 1/2, eg , you need to define size. one of the install/example has such a template. then, use char_library -auto_index. the tool will create all slew/load table for you to satisfy you defined max_transition.

I did not understand this, can you please explain this a little more? I already did these as you'd suggested them earlier.

I have already done this in template.tcl :

set_var min_transition 6e-12
set_var max_transition 1e-06
set_var min_output_cap 1e-16

Am I supposed to remove the power delay and constraint templates when I use -auto_index in char_library?

If required, am I allowed to request you for a short call?
Thanks

iamKarthikBK said:

set_var min_transition 6e-12
set_var max_transition 1e-06
set_var min_output_cap 1e-16

These will be used only if you have -auto_index in char_library command.

If you use -auto_index option, the actual slew/load table will be,

index_1 {value_of_min_transtion <other values> value_of_max_transition}

index_2 {min_output_cap ..... }. the largest load will give you a rise/fall transition (see your .lib) that is close to max_transition. This ensures a good quality of the .lib.

With auto_index flow, the actual values in your index_1/2 are not used. Only the size of the table matters. you may use {1 2 3 4 5} for a table with 5 indexes, which is NO different from {0.2 0.4 0.6 0.8 1} , or any table of 5 indexes.

The three variables are determined by your design specification, ie. the operating speed. Will your design be operated at a speed equivalent to 1e-6s ? The auto-calculated maximum load basically tells you the maximum driving capability you cell can have, without exceeding the max_transition.

As I have said, the installation directory has example of auto_index, or can be modified to do so. i suggest you play with the example to have better understanding.

Guangjun Cao said:

With auto_index flow, the actual values in your index_1/2 are not used. Only the size of the table matters. you may use {1 2 3 4 5} for a table with 5 indexes, which is NO different from {0.2 0.4 0.6 0.8 1} , or any table of 5 indexes.

Oh, okay!

Guangjun Cao said:

Will your design be operated at a speed equivalent to 1e-6s

Yes I am targeting 1MHz operation, if that's what you mean to ask.

Guangjun Cao said:

As I have said, the installation directory has example of auto_index, or can be modified to do so. i suggest you play with the example to have better understanding.

Well, yes I've been using that and the characterization just stops here:

---------- Entering compute template index ------------ May 22 19:25:28
May 22 19:25:28 Determining template indices...
(May 22 19:25:28) Begin of pre-driver matching trans.
(May 22 19:25:28) End of pre-driver matching trans.

Minimum transition index for the library: 6e-12 sec
Maximum transition index for the library: 2e-07 sec
Minimum output capacitance index for the library: 1e-16 F
May 22 19:25:40 Autoindex finished.
---------- Exiting compute template index ------------ May 22 19:25:40
MEM=487 MB
MEM=487 MB
(May 22 19:25:40) Generating vectors: AND2X1
(May 22 19:25:40) Generating vectors: INVX1
(May 22 19:25:40) Generating vectors: NAND2X1
(May 22 19:25:40) Generating vectors: NOR2X1
(May 22 19:25:40) Generating vectors: OR2X1
MEM=488 MB
(May 22 19:25:40) Begin of pre-driver matching trans.
Generating CCST predriver for 1 unique input transition times .
(May 22 19:25:40) End of pre-driver matching trans.

May 22 19:25:40 Thread 3: Cell=OR2X1 (0%) Pin= Related= combinational leakage_power
May 22 19:25:40 Thread 1: Cell=OR2X1 (0%) Pin= Related= combinational leakage_power
May 22 19:25:50 Thread 0: Cell=OR2X1 (0%) Pin= Related= combinational leakage_power
May 22 19:25:50 Thread 2: Cell=OR2X1 (0%) Pin= Related= combinational leakage_power

I'll just try to play around with it a little more

thanks

Hi again Guangjun Cao

I tried modifying the files in install/example/liberate and I was able to characterize the cells I needed.
The delay values seem right to me now (based on the max transition time I gave along with the auto_index option to char_library).

highpower_tt_1.8_25.txt and lowpower_tt_0.3_25.txt are the datasheets.
But I still see that the power values are 0, and area I do not know how to tell liberate.

How do I tell the area to liberate and how do I fix the power values that are being shown as 0?

I did this for highpower_tt_1.8_25

set_var min_transition 6e-12
set_var max_transition 50e-09
set_var min_output_cap 1e-16

I did this for lowpower_tt_0.3_25

set_var min_transition 6e-12
set_var max_transition 200e-09
set_var min_output_cap 1e-16

You might have already told this before, sorry I just couldn't catch along, if you already have, can you please mention it again?

Thanks

area and other attributes that are NOT from simulation results can be set set using set_attribute command.

The power for lowpower_tt_0.3_25 has more "0", seems to indicate this is precision-related. Try ldb_precision, write_library -precision, and search for "precision" in the PDF doc to find and tune related variables.

 For any power-related the debug, search for "power" in PDF DOC to find related tool variable. In any case, you may set power_info (check the PDF DOC for details) and check the standalone simulation results (you need extsim_save_passed and _failed set as deck). power is characterized using the same deck as delay/timing. check .meas statement in the deck and sim.measure file from the simulation. Power is calculated using integral of VDD/VSS current. going through power_info file and spectre simulation results, it is very easy to find out how the values are calcuted and put in the .lib.

Note: datasheet does not show you the full picture. .lib should be the first file to look at.

if the above suggestions do not help, contact customer support  team and provide a full test case.