Generating .lib file for synthesis using Genus from transistor level cells using Virtuoso

To do liberate characterization, you need post-layout netlist for each cell that need to be characterized. for this, you do not need a spectre view.

I see. Would you please elaborate a little bit as to how to generate a post layout netlist?

A post-layout netlist can be generated using physical verification tools, eg. Cadence Assura/QRC, PVS. Liberate accepts Spice/Spectre/DSPF formats.

I am using Assura Quantus for Parasitic Extraction, and I'm ending up with a few errors. Can you please help me understand as to where I could be going wrong?
Here is the log file

Cadence Quantus Extraction - 64-bit Parasitic Extractor - Version
20.1.1-s233 Wed Mar 25 13:13:47 PDT 2020
---------------------------------------------------------------------------------------------------------------
Copyright 2020 Cadence Design Systems,
Inc.

INFO (EXTQRCXOPT-243) : For Assura inputs, if the "output_setup -directory_name" option was not
specified, it is automatically set to the input directory.
INFO (LBRCXU-108): Starting

/home/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/__qrc.rcx_cmd -t -f /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/extview.tmp -w /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1
WARNING (LBRCXU-172): m2write fd 10, 1 tries, bytes -1 of 14, errno 9 Bad file descriptor

Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.11s.
@(#)$CDS: rcxToDfII_64 version av4.1:Production:dfII6.1.8-64b:IC6.1.8-64b.83 12/20/2018 04:06 (sjfib187) $
sub-version 4.1_USR6, integ signature 2018-12-20-0335

run on cad19 from /home/installs/ASSURA41/tools.lnx86/assura/bin/64bit/rcxToDfII on Mon May 10 16:01:04 2021

*WARNING* Technology must be specified!
Loading UMC_18_CMOS/loadCxt.ile ... done!
Loading context 'designrule' from library 'UMC_18_CMOS' ... done!
Loading context 'toolFunction' from library 'UMC_18_CMOS' ... done!
Loading context 'Callback_MM' from library 'UMC_18_CMOS' ... done!
Loading context 'Callback_RF' from library 'UMC_18_CMOS' ... done!
Loading context 'pcell' from library 'UMC_18_CMOS' ... done!
Loading context 'Util' from library 'UMC_18_CMOS' ... done!
Loading context 'update_pdps' from library 'UMC_18_CMOS' ... done!
Loading /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/UMC_18_CMOS/libInitCustomExit.il
*WARNING* (TECH-230035): User-defined rule "minExtensionDistance" in constraint
group "foundry" of techDB "UMC_18_CMOS" conflicts with
a built-in constraint with the same name.
You may write out "constraintGroups" section to an
ASCII file, reopen the technology database in "a"
mode, and reload the file to update the database.
Another option is to rename this rule.
*ERROR* No library model for device "N_18_G2".
*ERROR* No library model for device "P_18_G2".
*ERROR* No library model for device "N_33_G2".
*ERROR* No library model for device "P_33_G2".
*ERROR* No library model for device "NB".
*ERROR* No library model for device "N_PG400_G2".
*ERROR* No library model for device "N_PD400_G2".
*ERROR* No library model for device "P_L400_G2".
*ERROR* No library model for device "N_PG1020_G2".
*ERROR* No library model for device "N_PD1020_G2".
*ERROR* No library model for device "P_L1020_G2".
*ERROR* No library model for device "PB".
*ERROR* No library model for device "RSNWELL".
*ERROR* No library model for device "RSND".
*ERROR* No library model for device "RSPD".
*ERROR* No library model for device "RSNPO".
*ERROR* No library model for device "RSPPO".
*ERROR* No library model for device "RNND".
*ERROR* No library model for device "RNPD".
*ERROR* No library model for device "RNNPO".
*ERROR* No library model for device "RNPPO".
*ERROR* No library model for device "PNP_V50X50_G2".
*ERROR* No library model for device "PNP_V100X100_G2".
*ERROR* No library model for device "DION_G2".
*ERROR* No library model for device "DIOP_G2".
*ERROR* No library model for device "DIONW_G2".
*ERROR* No library model for device "RM1_MM".
*ERROR* No library model for device "RM2_MM".
*ERROR* No library model for device "RM3_MM".
*ERROR* No library model for device "RM4_MM".
*ERROR* No library model for device "RM5_MM".
*ERROR* No library model for device "RM6_MM".

ERROR: Assura is terminating because some library models do not exist.
Your rules and your dfII model libraries are inconsistent.
Assura requires all library models in the rule file be present
in the database when running rcx with the "extracted_view"
option.

INFO (LBRCXU-111): Warning /home/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII exit with bad status

INFO (LBRCXU-112): Warning Status 256

INFO (LBRCXU-113): Warning Quantus execution terminated

***** aveng fork terminated abnormally *****

please submit a case, so that an AE can help you debug on the settings for extraction.

My COS account is generated using a reference key instead of a host id, I am unable to file cases on cadence support :(

You probably need to check that this checkbox is turned off on the Quantus form:

I did that. I'm still getting errors, maybe these are related to the connections I have made?

Here's the log file:

Cadence Quantus Extraction - 64-bit Parasitic Extractor - Version
20.1.1-s233 Wed Mar 25 13:13:47 PDT 2020
---------------------------------------------------------------------------------------------------------------
Copyright 2020 Cadence Design Systems,
Inc.

INFO (EXTQRCXOPT-243) : For Assura inputs, if the "output_setup -directory_name" option was not
specified, it is automatically set to the input directory.
INFO (LBRCXU-108): Starting

/home/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/__qrc.rcx_cmd -t -f /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/extview.tmp -w /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1
WARNING (LBRCXU-172): m2write fd 10, 1 tries, bytes -1 of 14, errno 9 Bad file descriptor

Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.10s.
@(#)$CDS: rcxToDfII_64 version av4.1:Production:dfII6.1.8-64b:IC6.1.8-64b.83 12/20/2018 04:06 (sjfib187) $
sub-version 4.1_USR6, integ signature 2018-12-20-0335

run on cad19 from /home/installs/ASSURA41/tools.lnx86/assura/bin/64bit/rcxToDfII on Mon May 10 16:54:51 2021

*WARNING* Technology must be specified!
Loading UMC_18_CMOS/loadCxt.ile ... done!
Loading context 'designrule' from library 'UMC_18_CMOS' ... done!
Loading context 'toolFunction' from library 'UMC_18_CMOS' ... done!
Loading context 'Callback_MM' from library 'UMC_18_CMOS' ... done!
Loading context 'Callback_RF' from library 'UMC_18_CMOS' ... done!
Loading context 'pcell' from library 'UMC_18_CMOS' ... done!
Loading context 'Util' from library 'UMC_18_CMOS' ... done!
Loading context 'update_pdps' from library 'UMC_18_CMOS' ... done!
Loading /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/UMC_18_CMOS/libInitCustomExit.il
*WARNING* (TECH-230035): User-defined rule "minExtensionDistance" in constraint
group "foundry" of techDB "UMC_18_CMOS" conflicts with
a built-in constraint with the same name.
You may write out "constraintGroups" section to an
ASCII file, reopen the technology database in "a"
mode, and reload the file to update the database.
Another option is to rename this rule.
*WARNING* No library model for device "N_18_G2".
*WARNING* No library model for device "P_18_G2".
*WARNING* No library model for device "N_33_G2".
*WARNING* No library model for device "P_33_G2".
*WARNING* No library model for device "NB".
*WARNING* No library model for device "N_PG400_G2".
*WARNING* No library model for device "N_PD400_G2".
*WARNING* No library model for device "P_L400_G2".
*WARNING* No library model for device "N_PG1020_G2".
*WARNING* No library model for device "N_PD1020_G2".
*WARNING* No library model for device "P_L1020_G2".
*WARNING* No library model for device "PB".
*WARNING* No library model for device "RSNWELL".
*WARNING* No library model for device "RSND".
*WARNING* No library model for device "RSPD".
*WARNING* No library model for device "RSNPO".
*WARNING* No library model for device "RSPPO".
*WARNING* No library model for device "RNND".
*WARNING* No library model for device "RNPD".
*WARNING* No library model for device "RNNPO".
*WARNING* No library model for device "RNPPO".
*WARNING* No library model for device "PNP_V50X50_G2".
*WARNING* No library model for device "PNP_V100X100_G2".
*WARNING* No library model for device "DION_G2".
*WARNING* No library model for device "DIOP_G2".
*WARNING* No library model for device "DIONW_G2".
*WARNING* No library model for device "RM1_MM".
*WARNING* No library model for device "RM2_MM".
*WARNING* No library model for device "RM3_MM".
*WARNING* No library model for device "RM4_MM".
*WARNING* No library model for device "RM5_MM".
*WARNING* No library model for device "RM6_MM".
INFO (LBRCXU-114): Finished /home/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII

INFO (LBRCXM-642): Constructing the RCX run script

Forking: capgen -techdir /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/RuleDecks/Assura/LPE -inc /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1.elf -lvs /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1.xcn -lvsvia -p2lvs /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/RuleDecks/Assura/LPE/p2lvsfile -reseqn -sw3d -length_units meters -blocking RFSYMBOL,DIFF_diel,PSD_C,PLY_C,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,MMCTP_C,ME6_C -blocking cmmc_mm,ME5_C,MMCTP_C -blocking cmmc_msq_rf,ME5_C,MMCTP_C -res_blocking RFSYMBOL,ply,M1,M2,M3,M4,slm_c,MMC,top_m_c -res_blocking cmmc_msq_rf,slm_c,MMC -p PLY_C,Allgates,PSD_C -cap_unit 1 -mos_diff_ap_nw /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1

INFO (LBMISC-215205):
*** Cadence Quantus Extraction Techgen -trans VERSION 20.1.1 Linux 64 bit - (Wed Mar 25 13:13:47 PDT 2020) ***

INFO (CAPGEN-41199):

Techgen -trans results will be written to directory: /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1

INFO (CAPGEN-41737): Lvs layers STP ind_minus ind_plus qte rfnd rfns rfpd rfps slm_term are not mapped in layer_setup file

rcxspice took 0.48 user, 0.10 sys, 1.00 elapsed, 3932.0 kbytes

Successfully created RCX script '/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/rcx.sh'
WARNING (LBRCXM-617): Unable to obtain 1 license(s) of QTS100 20.10

INFO (LBRCXM-581): Checked out '1' license(s) of QTS300 20.10

INFO (LBRCXM-608): Executing command
/bin/ksh /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/rcx.sh

##=======================================================
##ADD_EXPLICIT_VIAS=N
##ADD_BULK_TERMINAL=N
##AGDS_FILE=/dev/null
##AGDS_LAYER_MAP_FILE=/dev/null
##HCCI_DEV_PROP_FILE=/dev/null
##AGDS_SPICE_FILE=/dev/null
##AGDS_TEXT_LAYERS=
##ARRAY_VIAS_SPACING=
##ASSURA_RUN_DIR=/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run
##ASSURA_RUN_NAME=INVX1
##BLACK_BOX_CELLS=/dev/null
##BREAK_WIDTH=
##CAP_COUPLING_FACTOR=1.0
##CAP_EXTRACT_MODE=coupled
##CAP_GROUND=gnd!
##CAP_MODELS=no
##DANGLINGR=N
##DENSITY_CHECK_METHOD=P
##DELETE_OUTPUT_FILE=N
##DEVICE_FINGER_DELIMITER='@'
##DF2=Y
##DRACULA_RUN_DIR=
##DRACULA_RUN_NAME=
##ENABLESENSITIVITYEXTRACTION=N
##EXCLUDE_FLOAT_LIMIT=
##EXCLUDE_FLOAT_DECOPULING_FACTOR=
##EXCLUDE_FLOATING_NETS=N
##EXCLUDE_NETS_REDUCERC=/dev/null
##EXCLUDE_SELF_CAPS=Y
##IGNORE_GATE_DIFFUSION_FRINGING_CAP=Y
##EXTRACT=both
##EXTRACT_MOS_DIFFUSION_AP=N
##EXTRACT_MOS_DIFFUSION_HIGH=
##EXTRACT_MOS_DIFFUSION_RES=N
##FILTER_SIZE=2.0
##FIXED_NETS_FILE=/dev/null
##FMAX=
##FRACTURE_LENGTH_UNITS=MICRONS
##FREQUENCY_FILE=/dev/null
##GROUND_NETS=
##GROUND_NETS_FILE=/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/qrc.GLOBAL.nets
##GROUND_SUBSTRATE_FLOATING_NETS=N
##HCCI_DEV_PROP=7
##HCCI_INST_PROP=6
##HCCI_NET_PROP=5
##HCCI_RULE_FILE=
##HCCI_RUN_DIR=
##HCCI_RUN_NAME=
##HEADER_FILE=/dev/null
##HIERARCHY_DELIMITER='/'
##OUTPUT_HIERARCHY_DELIMITER='/'
##HRCX_CELLS_FILE=/dev/null
##IMPORT_GLOBALS=Y
##LADDER_NETWORK=N
##LVS_SOURCE=assura
##M_FACTORR=
##M_FACTORW=N
##MACRO_CELL=Y
##MAX_FRACTURE_LENGTH=infinite
##MAX_SIGNALS=
##MERGE_PARALLEL_R=N
##MERGE_PARALLEL_VIA=N
##MINC=1e-17
##MINC_BY_PERCENTAGE=0.1
##MINR=0.001
##NET_NAME_SPACE=layout
##NETS_FILE=/dev/null
##OUTPUT=/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/extview.tmp
##OUTPUT_NET_NAME_SPACE=layout
##PARASITIC_BLOCKING_DEVICE_CELLS_TYPE=gray
##PARASITIC_CAP_MODELS=no
##PARASITIC_RES_MODELS=comment
##PARASITIC_RES_LENGTH=N
##PARASITIC_RES_WIDTH=N
##PARASITIC_RES_WIDTH_DRAWN=N
##PARASITIC_RES_UNIT=N
##PARTIAL_CAP_BLOCKING=N
##PEEC=N
##PIN_ORDER_FILE=/dev/null
##PIPE_ADVGEN=
##PIPE_SPICE2DB=
##POWER_NETS=
##POWER_NETS_FILE=/dev/null
##RC_FREQUENCY=
##RCXDIR=/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1
##RCXFS_HIGH=N
##RCXFS_NETS_FILE=
##RCXFS_TYPE=none
##RCXFS_CUTOFF_DISTANCE=
##RCXFS_CUTOFF_DISTANCE=
##RCXFS_CUTOFF_DISTANCE=
##RCXFS_CUTOFF_DISTANCE=
##RCXFS_CUTOFF_DISTANCE=
##RCXFS_VIA_OFF=N
##REDUCERC=N
##REGION_LIMIT=
##RES_MODELS=no
##RISE_TIME=
##SAVE_FILL_SHAPES=N
##SINGLE_CAP_EDSPF=N
##SHOW_DIODES=N
##SKIN_FREQUENCY=
##SPEF=N
##SPEF_UNITS=
##SPLIT_PINS=N
##FORCE_SUBCELL_PIN_ORDERS=N
##SPLIT_PINS_DISTANCE=
##SUB_NODE_CHAR='#'
##SUBSTRATE_PROFILE=/dev/null
##SUBSTRATE_STAMPING_OFF=N
##TEMPDIR=/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/rcx_temp
##TEMPERATURE=25.0
##TYPE=full
##USER_REGION=/dev/null
##VARIANT_CELL_FILE=/dev/null
##VIA_EFFECT_OFF=N
##VIRTUAL_FILL=
##XREF=/dev/null,/dev/null
##XY_COORDINATES=c,r
##=======================================================

CASE_SENSITIVE=TRUE
export CASE_SENSITIVE
QRC_MOS_LW_PRECISION=y
export QRC_MOS_LW_PRECISION
TEMPDIR=`setTempDir /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/rcx_temp`
setTempDir /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/rcx_temp
export TEMPDIR
DEVICE_FINGER_DELIMITER='@'
HIERARCHY_DELIMITER='/'
OUTPUT_HIERARCHY_DELIMITER='/'
cd /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1
cat <<ENDCAT> caps2dversion
* caps2d version: 10
ENDCAT
cat <<ENDCAT> flattransUnit.info
meters
ENDCAT
QRC=Y
export QRC
cat <<ENDCAT> topcellxcn.info
/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1.xcn
ENDCAT

#==========================================================#
# Generate RCX input data from Assura LVS database
#==========================================================#

GOALIE2DIR=/home/installs/QUANTUS201/tools.lnx86/extraction/bin
export GOALIE2DIR
vdbToRcx /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run INVX1 -unit \
meters -- -V1 -H satfile -r \
/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1.xcn -gl \
vdd,gnd -df2 -xgl
@(#)$CDS: vdbToRcx_64 version av4.1:Production:dfII6.1.8-64b:IC6.1.8-64b.83 12/20/2018 04:06 (sjfib187) $
18.2.0 Linux 64 bit - (Wed Aug 1 08:39:56 PDT 2018)
Opening LVS data for INVX1 in /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run
Open time is 0.0 sec.
Build pins/attributes took 0.0 sec.
Processing m1_textt 4 shapes 0.0 sec.
create satfile took 0.03 user, 0.01 sys, 0.00 elapsed, 134792.0 kbytes
write edge m1_textt took 0.00 user, 0.00 sys, 0.00 elapsed, 134856.0 kbytes
Building net map file. 0.0 sec.
create netmap file took 0.00 user, 0.00 sys, 0.00 elapsed, 134904.0 kbytes
create net file took 0.00 user, 0.00 sys, 0.00 elapsed, 134980.0 kbytes
WARNING (LBCLV-5663): No bipolar models provided. Can't create bipolar files

WARNING (LBCLV-5660): No resistor models provided. Can't create resistor files

WARNING (LBCLV-5654): No capacitor models provided. Can't create capacitor file

WARNING (LBCLV-5657): No diode models provided. Can't create diode files

WARNING (LBCLV-5706): no generic models in rule file

Device creation took 0.0 sec
Processing psdcon 13 shapes 0.0 sec.
write edge psdcon took 0.00 user, 0.00 sys, 0.00 elapsed, 135212.0 kbytes
Processing nsdcon 3 shapes 0.0 sec.
write edge nsdcon took 0.00 user, 0.00 sys, 0.00 elapsed, 135244.0 kbytes
Processing polycon 1 shapes 0.0 sec.
write edge polycon took 0.00 user, 0.00 sys, 0.00 elapsed, 135280.0 kbytes
write edge pgate_mm_MOS_28 took 0.00 user, 0.00 sys, 0.00 elapsed, 135328.0 kbytes
write edge ngate_mm_MOS_27 took 0.00 user, 0.00 sys, 0.00 elapsed, 135360.0 kbytes
Processing pgate_mm_MOS_28 1 shapes 0.0 sec.
Processing ngate_mm_MOS_27 1 shapes 0.0 sec.
Processing M1 4 shapes 0.0 sec.
write edge M1 took 0.00 user, 0.00 sys, 0.00 elapsed, 135456.0 kbytes
Processing ply 1 shapes 0.0 sec.
write edge ply took 0.00 user, 0.00 sys, 0.00 elapsed, 135488.0 kbytes
Processing ptap 1 shapes 0.0 sec.
write edge ptap took 0.00 user, 0.01 sys, 0.00 elapsed, 135524.0 kbytes
Processing ntap 1 shapes 0.0 sec.
write edge ntap took 0.00 user, 0.00 sys, 0.00 elapsed, 135556.0 kbytes
Processing nsd 3 shapes 0.0 sec.
write edge nsd took 0.00 user, 0.00 sys, 0.00 elapsed, 135588.0 kbytes
write edge RFSYMBOL took 0.00 user, 0.00 sys, 0.00 elapsed, 135592.0 kbytes
Processing RFSYMBOL 0 shapes 0.0 sec.
Processing psd 3 shapes 0.0 sec.
write edge psd took 0.00 user, 0.00 sys, 0.00 elapsed, 135620.0 kbytes
Processing wel 1 shapes 0.0 sec.
write edge wel took 0.00 user, 0.00 sys, 0.00 elapsed, 135652.0 kbytes
Processing psub 1 shapes 0.0 sec.
write edge psub took 0.00 user, 0.00 sys, 0.00 elapsed, 135684.0 kbytes
WARNING (LBCLV-5576): Ignoring duplicate layer-generation request of RFSYMBOL (id 14)

Processing RFSYMBOL 0 shapes 0.0 sec.
sort edges took 0.04 user, 0.11 sys, 0.00 elapsed, 1900.0 kbytes
sort edges and labels took 0.85 user, 0.16 sys, 2.00 elapsed, 135700.0 kbytes

vdbToRcx System Usage:
Elapsed: 2 seconds.
CPU: 0.1 seconds
Memory 41 Meg
GOALIE2DIR=/home/installs/QUANTUS201/tools.lnx86/extraction/bin/64bit/
export GOALIE2DIR
geom ngate_mm_MOS_27 nsd - ngate_mm_MOS_27,10,i,1
geom pgate_mm_MOS_28 psd - pgate_mm_MOS_28,10,i,1

#==========================================================#
# Generate power list
#==========================================================#

cat global.net > power_list

#==========================================================#
# Ensure vias do not extend beyond routing
#==========================================================#

geom -V polycon M1 ply - polycon_M1_ply,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3012.0 kbytes
geom -V nsdcon M1 nsd - nsdcon_M1_nsd,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3008.0 kbytes
geom -V nsdcon M1 ntap - nsdcon_M1_ntap,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3012.0 kbytes
geom -V nsdcon nsd ntap - nsdcon_nsd_ntap,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3008.0 kbytes
geom -V psdcon M1 psd - psdcon_M1_psd,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3008.0 kbytes
geom -V psdcon M1 ptap - psdcon_M1_ptap,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3008.0 kbytes
geom -V psdcon psd ptap - psdcon_psd_ptap,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3012.0 kbytes
geom -V psub ptap - psub_ptap_ovia,11,i,1
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2996.0 kbytes
geom -V wel ntap - wel_ntap_ovia,11,i,1

geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3000.0 kbytes
#==========================================================#
# Flatten net file, routing, via and device layers
#==========================================================#

SAVEDIR=`beginFlattenInputs`
beginFlattenInputs
export SAVEDIR
/bin/mv -f NET h_NET
flatnet -V -li -h '/' h_NET NET
flatnet took 0.00 user, 0.00 sys, 0.00 elapsed, 11828.0 kbytes
netprint -V -N1 power_list:power_list_nums NET
flattenTransistorData ngate_mm_MOS_27 meters
flattub took 0.00 user, 0.02 sys, 0.00 elapsed, 4564.0 kbytes
flatnet took 0.00 user, 0.00 sys, 0.00 elapsed, 11812.0 kbytes
flattenTransistorData pgate_mm_MOS_28 meters
flattub took 0.00 user, 0.00 sys, 0.00 elapsed, 4564.0 kbytes
flatnet took 0.00 user, 0.00 sys, 0.00 elapsed, 11812.0 kbytes
flattenLayers -m polycon nsdcon psdcon M1 ply nsd psd ntap ptap psub wel \
polycon_M1_ply nsdcon_M1_nsd nsdcon_M1_ntap nsdcon_nsd_ntap \
psdcon_M1_psd psdcon_M1_ptap psdcon_psd_ptap psub_ptap_ovia \
wel_ntap_ovia
flattub took 0.00 user, 0.00 sys, 0.00 elapsed, 3172.0 kbytes
endFlattenInputs

#==========================================================#
# Initialize CAP_GROUND variable
#==========================================================#

CAP_GROUND=`findCapGround -g gnd! NET`
findCapGround -g gnd! NET
ERROR (FINDCAP-88016): cap ground signal 'gnd!' cannot be found.
Check if net 'gnd!' exists in design and has the correct ?netNameSpace (schematic, layout) specified in RSF.
If the ground signal name cannot be identified, use 'capgen -cap_ground_layer' option.

ERROR (LBRCXM-609): Bad return status from RCX run. 0xff00

ERROR (LBRCXM-709): ***** Quantus terminated abnormally *****

I did that. I'm still getting errors, maybe these are related to the connections I have made?

Here's the log file:

Cadence Quantus Extraction - 64-bit Parasitic Extractor - Version
20.1.1-s233 Wed Mar 25 13:13:47 PDT 2020
---------------------------------------------------------------------------------------------------------------
Copyright 2020 Cadence Design Systems,
Inc.

INFO (EXTQRCXOPT-243) : For Assura inputs, if the "output_setup -directory_name" option was not
specified, it is automatically set to the input directory.
INFO (LBRCXU-108): Starting

/home/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/__qrc.rcx_cmd -t -f /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/extview.tmp -w /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1
WARNING (LBRCXU-172): m2write fd 10, 1 tries, bytes -1 of 14, errno 9 Bad file descriptor

Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.10s.
@(#)$CDS: rcxToDfII_64 version av4.1:Production:dfII6.1.8-64b:IC6.1.8-64b.83 12/20/2018 04:06 (sjfib187) $
sub-version 4.1_USR6, integ signature 2018-12-20-0335

run on cad19 from /home/installs/ASSURA41/tools.lnx86/assura/bin/64bit/rcxToDfII on Mon May 10 16:54:51 2021

*WARNING* Technology must be specified!
Loading UMC_18_CMOS/loadCxt.ile ... done!
Loading context 'designrule' from library 'UMC_18_CMOS' ... done!
Loading context 'toolFunction' from library 'UMC_18_CMOS' ... done!
Loading context 'Callback_MM' from library 'UMC_18_CMOS' ... done!
Loading context 'Callback_RF' from library 'UMC_18_CMOS' ... done!
Loading context 'pcell' from library 'UMC_18_CMOS' ... done!
Loading context 'Util' from library 'UMC_18_CMOS' ... done!
Loading context 'update_pdps' from library 'UMC_18_CMOS' ... done!
Loading /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/UMC_18_CMOS/libInitCustomExit.il
*WARNING* (TECH-230035): User-defined rule "minExtensionDistance" in constraint
group "foundry" of techDB "UMC_18_CMOS" conflicts with
a built-in constraint with the same name.
You may write out "constraintGroups" section to an
ASCII file, reopen the technology database in "a"
mode, and reload the file to update the database.
Another option is to rename this rule.
*WARNING* No library model for device "N_18_G2".
*WARNING* No library model for device "P_18_G2".
*WARNING* No library model for device "N_33_G2".
*WARNING* No library model for device "P_33_G2".
*WARNING* No library model for device "NB".
*WARNING* No library model for device "N_PG400_G2".
*WARNING* No library model for device "N_PD400_G2".
*WARNING* No library model for device "P_L400_G2".
*WARNING* No library model for device "N_PG1020_G2".
*WARNING* No library model for device "N_PD1020_G2".
*WARNING* No library model for device "P_L1020_G2".
*WARNING* No library model for device "PB".
*WARNING* No library model for device "RSNWELL".
*WARNING* No library model for device "RSND".
*WARNING* No library model for device "RSPD".
*WARNING* No library model for device "RSNPO".
*WARNING* No library model for device "RSPPO".
*WARNING* No library model for device "RNND".
*WARNING* No library model for device "RNPD".
*WARNING* No library model for device "RNNPO".
*WARNING* No library model for device "RNPPO".
*WARNING* No library model for device "PNP_V50X50_G2".
*WARNING* No library model for device "PNP_V100X100_G2".
*WARNING* No library model for device "DION_G2".
*WARNING* No library model for device "DIOP_G2".
*WARNING* No library model for device "DIONW_G2".
*WARNING* No library model for device "RM1_MM".
*WARNING* No library model for device "RM2_MM".
*WARNING* No library model for device "RM3_MM".
*WARNING* No library model for device "RM4_MM".
*WARNING* No library model for device "RM5_MM".
*WARNING* No library model for device "RM6_MM".
INFO (LBRCXU-114): Finished /home/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII

INFO (LBRCXM-642): Constructing the RCX run script

Forking: capgen -techdir /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/RuleDecks/Assura/LPE -inc /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1.elf -lvs /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1.xcn -lvsvia -p2lvs /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/RuleDecks/Assura/LPE/p2lvsfile -reseqn -sw3d -length_units meters -blocking RFSYMBOL,DIFF_diel,PSD_C,PLY_C,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,MMCTP_C,ME6_C -blocking cmmc_mm,ME5_C,MMCTP_C -blocking cmmc_msq_rf,ME5_C,MMCTP_C -res_blocking RFSYMBOL,ply,M1,M2,M3,M4,slm_c,MMC,top_m_c -res_blocking cmmc_msq_rf,slm_c,MMC -p PLY_C,Allgates,PSD_C -cap_unit 1 -mos_diff_ap_nw /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1

INFO (LBMISC-215205):
*** Cadence Quantus Extraction Techgen -trans VERSION 20.1.1 Linux 64 bit - (Wed Mar 25 13:13:47 PDT 2020) ***

INFO (CAPGEN-41199):

Techgen -trans results will be written to directory: /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1

INFO (CAPGEN-41737): Lvs layers STP ind_minus ind_plus qte rfnd rfns rfpd rfps slm_term are not mapped in layer_setup file

rcxspice took 0.48 user, 0.10 sys, 1.00 elapsed, 3932.0 kbytes

Successfully created RCX script '/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/rcx.sh'
WARNING (LBRCXM-617): Unable to obtain 1 license(s) of QTS100 20.10

INFO (LBRCXM-581): Checked out '1' license(s) of QTS300 20.10

INFO (LBRCXM-608): Executing command
/bin/ksh /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/rcx.sh

##=======================================================
##ADD_EXPLICIT_VIAS=N
##ADD_BULK_TERMINAL=N
##AGDS_FILE=/dev/null
##AGDS_LAYER_MAP_FILE=/dev/null
##HCCI_DEV_PROP_FILE=/dev/null
##AGDS_SPICE_FILE=/dev/null
##AGDS_TEXT_LAYERS=
##ARRAY_VIAS_SPACING=
##ASSURA_RUN_DIR=/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run
##ASSURA_RUN_NAME=INVX1
##BLACK_BOX_CELLS=/dev/null
##BREAK_WIDTH=
##CAP_COUPLING_FACTOR=1.0
##CAP_EXTRACT_MODE=coupled
##CAP_GROUND=gnd!
##CAP_MODELS=no
##DANGLINGR=N
##DENSITY_CHECK_METHOD=P
##DELETE_OUTPUT_FILE=N
##DEVICE_FINGER_DELIMITER='@'
##DF2=Y
##DRACULA_RUN_DIR=
##DRACULA_RUN_NAME=
##ENABLESENSITIVITYEXTRACTION=N
##EXCLUDE_FLOAT_LIMIT=
##EXCLUDE_FLOAT_DECOPULING_FACTOR=
##EXCLUDE_FLOATING_NETS=N
##EXCLUDE_NETS_REDUCERC=/dev/null
##EXCLUDE_SELF_CAPS=Y
##IGNORE_GATE_DIFFUSION_FRINGING_CAP=Y
##EXTRACT=both
##EXTRACT_MOS_DIFFUSION_AP=N
##EXTRACT_MOS_DIFFUSION_HIGH=
##EXTRACT_MOS_DIFFUSION_RES=N
##FILTER_SIZE=2.0
##FIXED_NETS_FILE=/dev/null
##FMAX=
##FRACTURE_LENGTH_UNITS=MICRONS
##FREQUENCY_FILE=/dev/null
##GROUND_NETS=
##GROUND_NETS_FILE=/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/qrc.GLOBAL.nets
##GROUND_SUBSTRATE_FLOATING_NETS=N
##HCCI_DEV_PROP=7
##HCCI_INST_PROP=6
##HCCI_NET_PROP=5
##HCCI_RULE_FILE=
##HCCI_RUN_DIR=
##HCCI_RUN_NAME=
##HEADER_FILE=/dev/null
##HIERARCHY_DELIMITER='/'
##OUTPUT_HIERARCHY_DELIMITER='/'
##HRCX_CELLS_FILE=/dev/null
##IMPORT_GLOBALS=Y
##LADDER_NETWORK=N
##LVS_SOURCE=assura
##M_FACTORR=
##M_FACTORW=N
##MACRO_CELL=Y
##MAX_FRACTURE_LENGTH=infinite
##MAX_SIGNALS=
##MERGE_PARALLEL_R=N
##MERGE_PARALLEL_VIA=N
##MINC=1e-17
##MINC_BY_PERCENTAGE=0.1
##MINR=0.001
##NET_NAME_SPACE=layout
##NETS_FILE=/dev/null
##OUTPUT=/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/extview.tmp
##OUTPUT_NET_NAME_SPACE=layout
##PARASITIC_BLOCKING_DEVICE_CELLS_TYPE=gray
##PARASITIC_CAP_MODELS=no
##PARASITIC_RES_MODELS=comment
##PARASITIC_RES_LENGTH=N
##PARASITIC_RES_WIDTH=N
##PARASITIC_RES_WIDTH_DRAWN=N
##PARASITIC_RES_UNIT=N
##PARTIAL_CAP_BLOCKING=N
##PEEC=N
##PIN_ORDER_FILE=/dev/null
##PIPE_ADVGEN=
##PIPE_SPICE2DB=
##POWER_NETS=
##POWER_NETS_FILE=/dev/null
##RC_FREQUENCY=
##RCXDIR=/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1
##RCXFS_HIGH=N
##RCXFS_NETS_FILE=
##RCXFS_TYPE=none
##RCXFS_CUTOFF_DISTANCE=
##RCXFS_CUTOFF_DISTANCE=
##RCXFS_CUTOFF_DISTANCE=
##RCXFS_CUTOFF_DISTANCE=
##RCXFS_CUTOFF_DISTANCE=
##RCXFS_VIA_OFF=N
##REDUCERC=N
##REGION_LIMIT=
##RES_MODELS=no
##RISE_TIME=
##SAVE_FILL_SHAPES=N
##SINGLE_CAP_EDSPF=N
##SHOW_DIODES=N
##SKIN_FREQUENCY=
##SPEF=N
##SPEF_UNITS=
##SPLIT_PINS=N
##FORCE_SUBCELL_PIN_ORDERS=N
##SPLIT_PINS_DISTANCE=
##SUB_NODE_CHAR='#'
##SUBSTRATE_PROFILE=/dev/null
##SUBSTRATE_STAMPING_OFF=N
##TEMPDIR=/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/rcx_temp
##TEMPERATURE=25.0
##TYPE=full
##USER_REGION=/dev/null
##VARIANT_CELL_FILE=/dev/null
##VIA_EFFECT_OFF=N
##VIRTUAL_FILL=
##XREF=/dev/null,/dev/null
##XY_COORDINATES=c,r
##=======================================================

CASE_SENSITIVE=TRUE
export CASE_SENSITIVE
QRC_MOS_LW_PRECISION=y
export QRC_MOS_LW_PRECISION
TEMPDIR=`setTempDir /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/rcx_temp`
setTempDir /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1/rcx_temp
export TEMPDIR
DEVICE_FINGER_DELIMITER='@'
HIERARCHY_DELIMITER='/'
OUTPUT_HIERARCHY_DELIMITER='/'
cd /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1
cat <<ENDCAT> caps2dversion
* caps2d version: 10
ENDCAT
cat <<ENDCAT> flattransUnit.info
meters
ENDCAT
QRC=Y
export QRC
cat <<ENDCAT> topcellxcn.info
/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1.xcn
ENDCAT

#==========================================================#
# Generate RCX input data from Assura LVS database
#==========================================================#

GOALIE2DIR=/home/installs/QUANTUS201/tools.lnx86/extraction/bin
export GOALIE2DIR
vdbToRcx /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run INVX1 -unit \
meters -- -V1 -H satfile -r \
/home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run/INVX1.xcn -gl \
vdd,gnd -df2 -xgl
@(#)$CDS: vdbToRcx_64 version av4.1:Production:dfII6.1.8-64b:IC6.1.8-64b.83 12/20/2018 04:06 (sjfib187) $
18.2.0 Linux 64 bit - (Wed Aug 1 08:39:56 PDT 2018)
Opening LVS data for INVX1 in /home/VLSI_ANALOG/UMC180/Designkits/Cadence_6.1/run
Open time is 0.0 sec.
Build pins/attributes took 0.0 sec.
Processing m1_textt 4 shapes 0.0 sec.
create satfile took 0.03 user, 0.01 sys, 0.00 elapsed, 134792.0 kbytes
write edge m1_textt took 0.00 user, 0.00 sys, 0.00 elapsed, 134856.0 kbytes
Building net map file. 0.0 sec.
create netmap file took 0.00 user, 0.00 sys, 0.00 elapsed, 134904.0 kbytes
create net file took 0.00 user, 0.00 sys, 0.00 elapsed, 134980.0 kbytes
WARNING (LBCLV-5663): No bipolar models provided. Can't create bipolar files

WARNING (LBCLV-5660): No resistor models provided. Can't create resistor files

WARNING (LBCLV-5654): No capacitor models provided. Can't create capacitor file

WARNING (LBCLV-5657): No diode models provided. Can't create diode files

WARNING (LBCLV-5706): no generic models in rule file

Device creation took 0.0 sec
Processing psdcon 13 shapes 0.0 sec.
write edge psdcon took 0.00 user, 0.00 sys, 0.00 elapsed, 135212.0 kbytes
Processing nsdcon 3 shapes 0.0 sec.
write edge nsdcon took 0.00 user, 0.00 sys, 0.00 elapsed, 135244.0 kbytes
Processing polycon 1 shapes 0.0 sec.
write edge polycon took 0.00 user, 0.00 sys, 0.00 elapsed, 135280.0 kbytes
write edge pgate_mm_MOS_28 took 0.00 user, 0.00 sys, 0.00 elapsed, 135328.0 kbytes
write edge ngate_mm_MOS_27 took 0.00 user, 0.00 sys, 0.00 elapsed, 135360.0 kbytes
Processing pgate_mm_MOS_28 1 shapes 0.0 sec.
Processing ngate_mm_MOS_27 1 shapes 0.0 sec.
Processing M1 4 shapes 0.0 sec.
write edge M1 took 0.00 user, 0.00 sys, 0.00 elapsed, 135456.0 kbytes
Processing ply 1 shapes 0.0 sec.
write edge ply took 0.00 user, 0.00 sys, 0.00 elapsed, 135488.0 kbytes
Processing ptap 1 shapes 0.0 sec.
write edge ptap took 0.00 user, 0.01 sys, 0.00 elapsed, 135524.0 kbytes
Processing ntap 1 shapes 0.0 sec.
write edge ntap took 0.00 user, 0.00 sys, 0.00 elapsed, 135556.0 kbytes
Processing nsd 3 shapes 0.0 sec.
write edge nsd took 0.00 user, 0.00 sys, 0.00 elapsed, 135588.0 kbytes
write edge RFSYMBOL took 0.00 user, 0.00 sys, 0.00 elapsed, 135592.0 kbytes
Processing RFSYMBOL 0 shapes 0.0 sec.
Processing psd 3 shapes 0.0 sec.
write edge psd took 0.00 user, 0.00 sys, 0.00 elapsed, 135620.0 kbytes
Processing wel 1 shapes 0.0 sec.
write edge wel took 0.00 user, 0.00 sys, 0.00 elapsed, 135652.0 kbytes
Processing psub 1 shapes 0.0 sec.
write edge psub took 0.00 user, 0.00 sys, 0.00 elapsed, 135684.0 kbytes
WARNING (LBCLV-5576): Ignoring duplicate layer-generation request of RFSYMBOL (id 14)

Processing RFSYMBOL 0 shapes 0.0 sec.
sort edges took 0.04 user, 0.11 sys, 0.00 elapsed, 1900.0 kbytes
sort edges and labels took 0.85 user, 0.16 sys, 2.00 elapsed, 135700.0 kbytes

vdbToRcx System Usage:
Elapsed: 2 seconds.
CPU: 0.1 seconds
Memory 41 Meg
GOALIE2DIR=/home/installs/QUANTUS201/tools.lnx86/extraction/bin/64bit/
export GOALIE2DIR
geom ngate_mm_MOS_27 nsd - ngate_mm_MOS_27,10,i,1
geom pgate_mm_MOS_28 psd - pgate_mm_MOS_28,10,i,1

#==========================================================#
# Generate power list
#==========================================================#

cat global.net > power_list

#==========================================================#
# Ensure vias do not extend beyond routing
#==========================================================#

geom -V polycon M1 ply - polycon_M1_ply,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3012.0 kbytes
geom -V nsdcon M1 nsd - nsdcon_M1_nsd,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3008.0 kbytes
geom -V nsdcon M1 ntap - nsdcon_M1_ntap,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3012.0 kbytes
geom -V nsdcon nsd ntap - nsdcon_nsd_ntap,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3008.0 kbytes
geom -V psdcon M1 psd - psdcon_M1_psd,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3008.0 kbytes
geom -V psdcon M1 ptap - psdcon_M1_ptap,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3008.0 kbytes
geom -V psdcon psd ptap - psdcon_psd_ptap,111,i,2
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3012.0 kbytes
geom -V psub ptap - psub_ptap_ovia,11,i,1
geom took 0.00 user, 0.00 sys, 0.00 elapsed, 2996.0 kbytes
geom -V wel ntap - wel_ntap_ovia,11,i,1

geom took 0.00 user, 0.00 sys, 0.00 elapsed, 3000.0 kbytes
#==========================================================#
# Flatten net file, routing, via and device layers
#==========================================================#

SAVEDIR=`beginFlattenInputs`
beginFlattenInputs
export SAVEDIR
/bin/mv -f NET h_NET
flatnet -V -li -h '/' h_NET NET
flatnet took 0.00 user, 0.00 sys, 0.00 elapsed, 11828.0 kbytes
netprint -V -N1 power_list:power_list_nums NET
flattenTransistorData ngate_mm_MOS_27 meters
flattub took 0.00 user, 0.02 sys, 0.00 elapsed, 4564.0 kbytes
flatnet took 0.00 user, 0.00 sys, 0.00 elapsed, 11812.0 kbytes
flattenTransistorData pgate_mm_MOS_28 meters
flattub took 0.00 user, 0.00 sys, 0.00 elapsed, 4564.0 kbytes
flatnet took 0.00 user, 0.00 sys, 0.00 elapsed, 11812.0 kbytes
flattenLayers -m polycon nsdcon psdcon M1 ply nsd psd ntap ptap psub wel \
polycon_M1_ply nsdcon_M1_nsd nsdcon_M1_ntap nsdcon_nsd_ntap \
psdcon_M1_psd psdcon_M1_ptap psdcon_psd_ptap psub_ptap_ovia \
wel_ntap_ovia
flattub took 0.00 user, 0.00 sys, 0.00 elapsed, 3172.0 kbytes
endFlattenInputs

#==========================================================#
# Initialize CAP_GROUND variable
#==========================================================#

CAP_GROUND=`findCapGround -g gnd! NET`
findCapGround -g gnd! NET
ERROR (FINDCAP-88016): cap ground signal 'gnd!' cannot be found.
Check if net 'gnd!' exists in design and has the correct ?netNameSpace (schematic, layout) specified in RSF.
If the ground signal name cannot be identified, use 'capgen -cap_ground_layer' option.

ERROR (LBRCXM-609): Bad return status from RCX run. 0xff00

ERROR (LBRCXM-709): ***** Quantus terminated abnormally *****

Here are screenshots if in case the net names are confusing :)

I haven't named the nets as 'gnd!' but only as 'gnd'. Same with 'vdd' being named as 'vdd!'. Andrew Beckett Guangjun Cao can you please tell me as to why that happens? 
What does /S_mustGroup_0/vdd! and /D_mustGroup_1/gnd! mean?

I am using UMC's 180nm FDK
Thank you so much for your time and patience in advance, I sincerely appreciate it!

I'm not sure why the nets have been named with a "global" suffix (the explanation mark) when the schematic has non-global names. I don't have access to that PDK (which is why this should go through customer support; then an AE who has time to explore this can take a look). I suspect that the Quantus error is that. you should probably be specifying the reference node as "gnd"; given that you've not shown your Quantus setup, it's hard to know for certain.

Usually for academic institutions you can either (if part of the Europractice scheme) contact Europractice support, or for Universities elsewhere your university contact (usually the professor who looks after the scheme) can log support questions on your behalf. Individual students only get the reference key access so that you can search issues, look at solutions, and access other material, but you can't create support cases directly (it needs to go through the filter of the coordinator at your university first to ensure that questions that can be handled locally first, can be).

Andrew

This issue was resolved! The reference net had to be set as 'gnd' instead of gnd!
It was my fault in the configuration!


Thank you so much!

Yes the reference node was gnd! instead of gnd. Thank you so much! this got resolved!

Yes we have access to UMC's FDK through the Europractice Consoritum. I will ask my co-ordinator to file a case with Cadence SUpport. Thank you once again :)

Hello Karthik,

Were you able to use the created standard cell library(.lib) in the Genus to synthesize the design?

I still haven't been able to generate the .lib file
Here's the latest update : community.cadence.com/.../1375478

thanks

I was able to generate the .lib file successfully by following this  run_char.tgz  downloaded from the link
https://support.cadence.com/apex/articleattachmentportal?id=a1O0V000007MgZLUA0&pageName=ArticleContent&attachId=0690V000003xCZjQAM&sq=null&caseSessionKey=null
and just modify the 
char.tcl
template.tcl
cells.tcl
userdata.lib accordingly.
And put your generated netlist file in the 'netlist' folder.
Place your spectre model files inside the 'models' folder.
I hope this helps.

Ponde Manoj Kumar said:

I hope this helps.

Thanks, I'll try this one out.

Ponde Manoj Kumar said:

userdata.lib accordingly.

Hi, Sorry I don't exactly know how to generate this file for my cells. I am assuming this has something to do with the layout, can you please tell me how I can generate this file for the selected cells?

I read this https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/41157/importing-standard-cell-area-into-lib-file-automatically and they say you need to generate the liberty file first.

I was able to generate the LEF file from Virtuoso (using av_extracted as the cell view). How do I go about telling liberate about the area of my cells?

Thanks