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SystemVerilog Outputs Incorrect Real Datatype Number Precision

Nader Fathy

Hello, 

I am using Virtuoso IC6.1.8-64b.500.23, Spectre 21.1.0.303.isr5, and Xcelium 21.09-s005 with AMS simulator. 

I have a simple SystemVerilog code as shown below to test output precision:

module test_blk1 (out1, out2 );
    output real out1, out2;
    assign out1 = 0.1;
    assign out2 = 0.0001;
endmodule

On simulating this with AMS simulator in a schematic view as shown below, the output of out1 is correct while out2 is zero!

Why is the "real - 64bit" precision not presented correctly in Virtuoso?

Any help is much appreciated.

Kindest Regards

Nader Fathy

  • Nader Fathy

    If you find yourself here, here is the solution I found:

    After doing some reading, SV precision is controlled by the connect rules, there is a module called connect E2R #(.vdelta(`Vdelta), .vtol(`Vdelta_tol), .ttol(`Tr_delta)); the variable Vdelta is set by default to have 6-bits precision in the old connect rules provided by Cadence. You will find it defined as `define Vdelta `Vsup/64. Change this a suitable precision you need, in my case I needed 20-bits of precision to build a DAC so I set it to `define Vdelta `Vsup/1048576

  • Andrew Beckett
    in reply to Nader Fathy

    This was covered in these two threads:

    They explain how to change the vdelta from the UI in ADE rather than needing to modify the connect rules (can also be done with an ie card in the command line flow), although of course you can also modify the connect rules.

    Andrew

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