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Buses in spectreText when creating symbol

MC20250412421

Hello everyone,

This is a repeat of this question but since no one answered I thought I could ask it again.
If there are multiple pins A_0, A_1, A_2 in a spectreText view, can you merge them so that the symbol generated from this view shows a unique pin A<2:0> ?

This is basically having something analogous to the schematic view where it is possible to create bus pins like A<2:0> and the symbol would automatically include such pins.

Thanks in advance for your responses and have a great day !

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  • Andrew Beckett

    If you can change the subckt names to be as follows (note the escaped angle-brackets):

    subckt textbus op bus\<3\> bus\<2\> bus\<1\> bus\<0\>
    r1 (bus\<3\> op) resistor r=1k
    r2 (bus\<2\> op) resistor r=1k
    r3 (bus\<1\> op) resistor r=1k
    r4 (bus\<0\> op) resistor r=1k

    ends textbus

    Then you will be offered to create a symbol with these names:

    op bus<3> bus<2> bus<1> bus<0>

    It's then easy to change to:

    op bus<3:0>

    but what will happen is that the terminal order will be recorded so that it knows the order they appear in in the subckt and so the netlist will be done correctly. For this to work, it really needs the names to be an expanded bus name syntax, whereas A_0, A_1 etc doesn't express any meaningful bus mapping from the A<3:0> to individual bits.

    That's probably the best approach. The challenge is that Spectre (like SPICE) does not have a bus syntax itself - so you need to ensure the names match what ADE would have netlisted them as.

    Andrew

Reply
  • Andrew Beckett

    If you can change the subckt names to be as follows (note the escaped angle-brackets):

    subckt textbus op bus\<3\> bus\<2\> bus\<1\> bus\<0\>
    r1 (bus\<3\> op) resistor r=1k
    r2 (bus\<2\> op) resistor r=1k
    r3 (bus\<1\> op) resistor r=1k
    r4 (bus\<0\> op) resistor r=1k

    ends textbus

    Then you will be offered to create a symbol with these names:

    op bus<3> bus<2> bus<1> bus<0>

    It's then easy to change to:

    op bus<3:0>

    but what will happen is that the terminal order will be recorded so that it knows the order they appear in in the subckt and so the netlist will be done correctly. For this to work, it really needs the names to be an expanded bus name syntax, whereas A_0, A_1 etc doesn't express any meaningful bus mapping from the A<3:0> to individual bits.

    That's probably the best approach. The challenge is that Spectre (like SPICE) does not have a bus syntax itself - so you need to ensure the names match what ADE would have netlisted them as.

    Andrew

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