Custom IC Design

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Discussion

Transient Noise Simulation in Spectre

Category: Custom IC Design

By SwatiSingh

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updated over 7 years ago by Karel Z

6 replies • 22041 views
Discussion

How can you change the waveform viewer defaults to thicker lines and not dotted?

Category: Custom IC Design

By CADcasualty

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updated over 7 years ago by CADcasualty

6 replies • 20943 views
Discussion

Is there any way to add a new empty strip on ViVa?

Category: Custom IC Design

By BaaB

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updated over 7 years ago by Andrew Beckett

3 replies • 14739 views
Discussion

What's the difference between 'all' and 'allpub' in the save options form of ADE L?

Category: Custom IC Design

By Cambridge Lv

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updated over 7 years ago by Cambridge Lv

2 replies • 9050 views
Discussion

Suggestions for practical ADE Assembler test setup for corner-specific cellviews?

Category: Custom IC Design

By hchan

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updated over 7 years ago by hchan

4 replies • 15326 views
Discussion

Cascaded display.drf loading

Category: Custom IC Design

By CADcasualty

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updated over 7 years ago by Andrew Beckett

6 replies • 26615 views
Discussion

how to run skill script from csh

Category: Custom IC Design

By qkoyote

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updated over 7 years ago by qkoyote

3 replies • 16344 views
Discussion

Post-simulation error

Category: Custom IC Design

By tahm

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updated over 7 years ago by Andrew Beckett

3 replies • 15755 views
Discussion

How to use a component (VerilogA) within a .scs model file to drive output signals

Category: Custom IC Design

By MT13

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updated over 7 years ago by MT13

7 replies • 18518 views
Discussion

ERROR (SFE-23): "input.scs" 19: X0 is an instance of an undefined model f_opAmp.

Category: Custom IC Design

By Jaisal

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updated over 7 years ago by Nicolas Callens

1 replies • 2807 views
Discussion

Filter Layout pins from LVS

Category: Custom IC Design

By PietroUser

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updated over 7 years ago by Andrew Beckett

3 replies • 14565 views
Discussion

Will different save options cause different Spectre simulation time?

Category: Custom IC Design

By Cambridge Lv

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updated over 7 years ago by Cambridge Lv

2 replies • 1357 views
Discussion

how to enforce identical MC mismatch variation on sub circuit used for calibration as those applied on the main test bench

Category: Custom IC Design

By HansB

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updated over 7 years ago by HansB

2 replies • 14264 views
Discussion

Device parameters not netlisting in LVS

Category: Custom IC Design

By analogmatch

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started over 7 years ago

0 replies • 13774 views
Discussion

Cadence simulation setup－core usage-

Category: Custom IC Design

By AllenD

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updated over 7 years ago by Andrew Beckett

3 replies • 3182 views

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