Custom IC Design

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Discussion

Author and library name in sheet border

Category: Custom IC Design

By DomiHammerfall

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updated over 1 year ago by DomiHammerfall

2 replies • 4328 views
Discussion

Error using probe terminal for dspf stb analysis

Category: Custom IC Design

By unSkilled

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updated over 1 year ago by Andrew Beckett

1 replies • 4560 views
Discussion

Change code in veriloga view from external program

Category: Custom IC Design

By mikewu999

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updated over 1 year ago by Andrew Beckett

1 replies • 3586 views
Discussion

Verilog-A: Can I ignore WARNING (VACOMP-1047)

Category: Custom IC Design

By mikewu999

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updated over 1 year ago by Andrew Beckett

1 replies • 3948 views
Discussion

Transient Simulation waveform abnormal

Category: Custom IC Design

By SkkyLee

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updated over 1 year ago by hayess

1 replies • 3769 views
Discussion

Xcelium/Simvision/xrun running very slow (waiting for SimVision/Verisium Debug to connect...)

Category: Custom IC Design

By MT202407295352

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started over 1 year ago

0 replies • 1361 views
Discussion

How to use PSpice library in Virtuoso/Spectre?

Category: Custom IC Design

By Jason Lee

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started over 1 year ago

0 replies • 616 views
Discussion

How can I place stacked vias with the size exact same cut width without metals around?

Category: Custom IC Design

By TzuYun Chang

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updated over 1 year ago by TzuYun Chang

2 replies • 3827 views
Discussion

Config sweep View in Tests

Category: Custom IC Design

By Mooh

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started over 1 year ago

0 replies • 3318 views
Discussion

Cannot access individual noise contributions using SpectreMDL

Category: Custom IC Design

By Carmi

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started over 1 year ago

0 replies • 3198 views
Discussion

New CDF creation and callback

Category: Custom IC Design

By IM202410225248

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started over 1 year ago

0 replies • 3305 views
Discussion

spectre 241 vs 211

Category: Custom IC Design

By kenc184

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updated over 1 year ago by kenc184

2 replies • 4214 views
Discussion

A problem with setup when Monte Carlo simulation starts

Category: Custom IC Design

By Mdad

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started over 1 year ago

0 replies • 3367 views
Discussion

Import LEF file failed due to layermap

Category: Custom IC Design

By TzuYun Chang

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started over 1 year ago

0 replies • 3811 views
Discussion

Netlisting error when doing parametric sweep on transient simulation

Category: Custom IC Design

By Volker T

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updated over 1 year ago by Volker T

1 replies • 4202 views

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