Custom IC Design

Latest Posts

Discussion

Suggestions for practical ADE Assembler test setup for corner-specific cellviews?

Category: Custom IC Design

By hchan

$usertype
•
updated over 7 years ago by hchan

4 replies • 15077 views
Discussion

Cascaded display.drf loading

Category: Custom IC Design

By CADcasualty

$usertype
•
updated over 7 years ago by Andrew Beckett

6 replies • 26281 views
Discussion

how to run skill script from csh

Category: Custom IC Design

By qkoyote

$usertype
•
updated over 7 years ago by qkoyote

3 replies • 16129 views
Discussion

Post-simulation error

Category: Custom IC Design

By tahm

$usertype
•
updated over 7 years ago by Andrew Beckett

3 replies • 15539 views
Discussion

How to use a component (VerilogA) within a .scs model file to drive output signals

Category: Custom IC Design

By MT13

$usertype
•
updated over 7 years ago by MT13

7 replies • 18229 views
Discussion

ERROR (SFE-23): "input.scs" 19: X0 is an instance of an undefined model f_opAmp.

Category: Custom IC Design

By Jaisal

$usertype
•
updated over 7 years ago by Nicolas Callens

1 replies • 2771 views
Discussion

Filter Layout pins from LVS

Category: Custom IC Design

By PietroUser

$usertype
•
updated over 7 years ago by Andrew Beckett

3 replies • 14366 views
Discussion

Will different save options cause different Spectre simulation time?

Category: Custom IC Design

By Cambridge Lv

$usertype
•
updated over 7 years ago by Cambridge Lv

2 replies • 1324 views
Discussion

how to enforce identical MC mismatch variation on sub circuit used for calibration as those applied on the main test bench

Category: Custom IC Design

By HansB

$usertype
•
updated over 7 years ago by HansB

2 replies • 14052 views
Discussion

Device parameters not netlisting in LVS

Category: Custom IC Design

By analogmatch

$usertype
•
started over 7 years ago

0 replies • 13593 views
Discussion

Cadence simulation setup－core usage-

Category: Custom IC Design

By AllenD

$usertype
•
updated over 7 years ago by Andrew Beckett

3 replies • 3104 views
Discussion

Liberate for .lib generation of D flip flop

Category: Custom IC Design

By anandmohan

$usertype
•
updated over 7 years ago by anandmohan

2 replies • 15877 views
Discussion

PAC + PSS for a single-inductor multiple-output (SIMO) converter with verilogA

Category: Custom IC Design

By BaaB

$usertype
•
updated over 7 years ago by BaaB

2 replies • 13770 views
Discussion

Changing x-value of a signal and/or handle signals with multiple outputs

Category: Custom IC Design

By itos

$usertype
•
updated over 7 years ago by Andrew Beckett

3 replies • 2743 views
Discussion

PSS not completing in post extraction design

Category: Custom IC Design

By praveenmv

$usertype
•
updated over 7 years ago by Dimitra Papazoglou

4 replies • 16774 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.