Custom IC Design

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Running worst case corners from ADEXL

Category: Custom IC Design

By NorNand

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updated over 5 years ago by NorNand

2 replies • 15266 views
Discussion

Pole Zero location from stb Analysis

Category: Custom IC Design

By Jaikrishnan

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updated over 5 years ago by Jaikrishnan

2 replies • 14777 views
Discussion

mosfet model spice/pspice

Category: Custom IC Design

By RobinCommander

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updated over 5 years ago by RobinCommander

6 replies • 5293 views
Discussion

There are several pwl sources in one file.

Category: Custom IC Design

By dressler6

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updated over 5 years ago by Andrew Beckett

1 replies • 16858 views
Discussion

Simulation failed, cannot compile ahdl libraries

Category: Custom IC Design

By Kabal

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updated over 5 years ago by Andrew Beckett

10 replies • 21240 views
Discussion

How we can use the single VCVS file containing N waveforms for generating the N voltage waveform sources in ADE-XL ?

Category: Custom IC Design

By RFStuff

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updated over 5 years ago by Andrew Beckett

3 replies • 17296 views
Discussion

Way to use SKILL script to save WAVEFORM into a file in ADE-XL Run

Category: Custom IC Design

By RFStuff

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updated over 5 years ago by Andrew Beckett

5 replies • 22262 views
Discussion

Simulation output results showing different names for the Expression used to calculate

Category: Custom IC Design

By Jaikrishnan

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updated over 5 years ago by Jaikrishnan

4 replies • 14835 views
Discussion

Avoid exporting .gi signals in Ocean

Category: Custom IC Design

By zaratustra

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updated over 5 years ago by FormerMember

3 replies • 14069 views
Discussion

[Spectre] multiple dynamic parameters ?

Category: Custom IC Design

By skylink

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updated over 5 years ago by FormerMember

7 replies • 21193 views
Discussion

VHDL-AMS delayed attribute

Category: Custom IC Design

By LukiLeu

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started over 5 years ago

0 replies • 13716 views
Discussion

Using one expression value to get another expression in ADE-L

Category: Custom IC Design

By Jaikrishnan

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updated over 5 years ago by Jaikrishnan

6 replies • 21820 views
Discussion

Force minimum 2 Vias whenever creating Via in Layout View

Category: Custom IC Design

By quyleanh

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started over 5 years ago

0 replies • 13300 views
Discussion

Transistors Operating Region check in Ocean Script

Category: Custom IC Design

By AtaV

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updated over 5 years ago by FormerMember

2 replies • 14945 views
Discussion

Import/exporting from cadence calculator

Category: Custom IC Design

By AtaV

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updated over 5 years ago by Andrew Beckett

1 replies • 2960 views

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