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Custom IC Design

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  • Discussion

    Why does renaming a file on Cadence Virtuoso take so much time?

    Category: Custom IC Design

    By Venn

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    updated over 7 years ago by Andrew Beckett

    1 replies • 15818 views
  • Discussion

    Is there a way to generate Gaussian random numbers in Ocean/Skill?

    Category: Custom IC Design

    By CADcasualty

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    •

    updated over 7 years ago by Andrew Beckett

    5 replies • 5010 views
  • Discussion

    Import from Synopsys IC Compiler to Virtuoso

    Category: Custom IC Design

    By MoMiner1870

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    •

    updated over 7 years ago by Andrew Beckett

    6 replies • 19207 views
  • Discussion

    QRC: *Error* load: can't access file "[...]/ext_18.12.000/tools/extraction/bin/32bit/etc/context/6.1.0/qrc.ini"

    Category: Custom IC Design

    By dontpanic

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    •

    updated over 7 years ago by dontpanic

    14 replies • 7935 views
  • Discussion

    Maximum metal length and single connection routing in Layout XL

    Category: Custom IC Design

    By farhan89

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    •

    started over 7 years ago

    0 replies • 14162 views
  • Discussion

    Auto-select spectre model for all simulations

    Category: Custom IC Design

    By MatthewLove

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    •

    updated over 7 years ago by MatthewLove

    2 replies • 13901 views
  • Discussion

    Multiple Via Cut Spacing for same ViaDefName

    Category: Custom IC Design

    By FormerMember

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    •

    started over 7 years ago

    0 replies • 2192 views
  • Discussion

    Auto routing constraints in cadence virtuoso

    Category: Custom IC Design

    By farhan89

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    •

    started over 7 years ago

    0 replies • 14163 views
  • Discussion

    probing signal in av_extracted_RC

    Category: Custom IC Design

    By HansB

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    •

    updated over 7 years ago by Quek

    3 replies • 13892 views
  • Discussion

    Multi-Voltage domain pin checks at schematic level

    Category: Custom IC Design

    By Johanny Saenz

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    •

    started over 7 years ago

    0 replies • 13790 views
  • Discussion

    Checking installation of PDK is correct

    Category: Custom IC Design

    By CxD7

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    •

    updated over 7 years ago by CxD7

    2 replies • 17300 views
  • Discussion

    CDF parameters reusing default value from veriloga

    Category: Custom IC Design

    By ernie123

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    •

    updated over 7 years ago by ernie123

    2 replies • 15000 views
  • Discussion

    APS: better Hyperthreading ON or OFF on the machine?

    Category: Custom IC Design

    By dontpanic

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    •

    updated over 7 years ago by dontpanic

    4 replies • 16150 views
  • Discussion

    Library Manager: .cdsenv / .cdsinit settings not taking effect

    Category: Custom IC Design

    By dontpanic

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    •

    updated over 7 years ago by dontpanic

    4 replies • 25196 views
  • Discussion

    design kits for a new member in cadence

    Category: Custom IC Design

    By tashtoush

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    •

    updated over 7 years ago by tashtoush

    6 replies • 16556 views
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