Custom IC Design

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Discussion

Ocean command to access the result stored during Monte-carlo Simulation

Category: Custom IC Design

By Ishant Anand

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updated over 7 years ago by Andrew Beckett

3 replies • 15932 views
Discussion

Deleting multiple instances of a cell from Layout

Category: Custom IC Design

By kash022

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updated over 7 years ago by kash022

4 replies • 17301 views
Discussion

Schematic editor: how to change the color of the annotations?

Category: Custom IC Design

By dontpanic

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updated over 7 years ago by dontpanic

2 replies • 17631 views
Discussion

Plot Schematic Hierarchy into single file

Category: Custom IC Design

By HoWei

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updated over 7 years ago by HoWei

3 replies • 16454 views
Discussion

Monte Carlo simulation results have difference even in ideal circuits

Category: Custom IC Design

By sam jiang

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updated over 7 years ago by Andrew Beckett

1 replies • 13981 views
Discussion

How to add/configure new column in Monte Carlo result page (Summary & Yield), like Std Dev/mean

Category: Custom IC Design

By sjwprc

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updated over 7 years ago by Andrew Beckett

1 replies • 756 views
Discussion

How to write Monte Carlo file for FinFET?

Category: Custom IC Design

By Amin Zayed

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updated over 7 years ago by Andrew Beckett

1 replies • 13803 views
Discussion

Reversing the contents of an expanded bus in VIVA

Category: Custom IC Design

By CADcasualty

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updated over 7 years ago by Andrew Beckett

2 replies • 14386 views
Discussion

Documentation error for awvPlotWaveform function in Virtuoso Visualization and Analysis XL SKILL Reference manual

Category: Custom IC Design

By CADcasualty

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updated over 7 years ago by Andrew Beckett

2 replies • 14041 views
Discussion

Simulation and PEX

Category: Custom IC Design

By AllenD

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updated over 7 years ago by Andrew Beckett

1 replies • 16506 views
Discussion

RE: IBIS Version 6.1

Category: Custom IC Design

By kenambo

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started over 7 years ago

0 replies • 13295 views
Discussion

Skill command to delete label from layout

Category: Custom IC Design

By Ishant Anand

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updated over 7 years ago by Andrew Beckett

1 replies • 16428 views
Discussion

Creating a CNTFET model in cadence using veriloga

Category: Custom IC Design

By nikita6

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updated over 7 years ago by Shobhitkareer

1 replies • 15531 views
Discussion

Auto route STOP at symbol boundary?

Category: Custom IC Design

By goofycat

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updated over 7 years ago by Andrew Beckett

1 replies • 13805 views
Discussion

Extend schematic Check&Save for checking instance CDF parameter

Category: Custom IC Design

By HoWei

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updated over 7 years ago by Andrew Beckett

1 replies • 1085 views

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