Custom IC Design

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Discussion

Is it required a particular license to plot internal VerilogA parameters?

Category: Custom IC Design

By Rawcode

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updated over 2 years ago by Rawcode

11 replies • 11980 views
Discussion

Instance bBox vs Flattened bBox

Category: Custom IC Design

By Chanyou

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updated over 2 years ago by Chanyou

1 replies • 7032 views
Discussion

how to set the default number of digits in the sim log

Category: Custom IC Design

By sjwprcker

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updated over 2 years ago by sjwprcker

2 replies • 7741 views
Discussion

will the phase of the pss period affect sampled pnoise result? can I control the pss phase?

Category: Custom IC Design

By Ring Lewis

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updated over 2 years ago by Ring Lewis

2 replies • 8060 views
Discussion

Running corner PVT sims with scalar output evaluated but waveforms not saved

Category: Custom IC Design

By SunnyBhagia

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updated over 2 years ago by ShawnLogan

4 replies • 8446 views
Discussion

error in digital verilog code

Category: Custom IC Design

By blossom

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updated over 2 years ago by Andrew Beckett

2 replies • 9356 views
Discussion

How to replace the device instance numbers

Category: Custom IC Design

By ichiro

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updated over 2 years ago by Andrew Beckett

3 replies • 8085 views
Discussion

Font Size for Trace Info Overlay in ViVA

Category: Custom IC Design

By jdsherman

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updated over 2 years ago by Andrew Beckett

2 replies • 7485 views
Discussion

RFpro-cadence interface

Category: Custom IC Design

By SreekanthIISc

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updated over 2 years ago by engrvip

2 replies • 8839 views
Discussion

QRC error undefined symbol: _ztin12openaccess_418oaconflictobserverins_8oaappdefelj0eee

Category: Custom IC Design

By KhaledHasan

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updated over 2 years ago by Andrew Beckett

1 replies • 1271 views
Discussion

ADE corner setup: Can I define a parametric set there?

Category: Custom IC Design

By StephanWeber

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updated over 2 years ago by Andrew Beckett

4 replies • 9866 views
Discussion

gpdk045 substrate file

Category: Custom IC Design

By SreekanthIISc

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updated over 2 years ago by Andrew Beckett

1 replies • 7827 views
Discussion

AMD EPYC processors and Cadence support

Category: Custom IC Design

By sysops

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started over 2 years ago

0 replies • 6833 views
Discussion

open a file and write in it (Verilog-A)

Category: Custom IC Design

By Hagar Hendy

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updated over 2 years ago by Hagar Hendy

1 replies • 7805 views
Discussion

Trouble with automatic route

Category: Custom IC Design

By TigerLi

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updated over 2 years ago by TigerLi

1 replies • 7051 views

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