Custom IC Design

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Discussion

Retaining group membership when copying fig group objects with "Transparent Group" set to "ON"

Category: Custom IC Design

By Jeff Lucas

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updated over 3 years ago by Andrew Beckett

1 replies • 1497 views
Discussion

HOW TO CALCULATE CLOCK FREQUENCY OF VPWL VOLTAGE SOURCE

Category: Custom IC Design

By rijalomkar

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updated over 3 years ago by Andrew Beckett

1 replies • 8566 views
Discussion

Ignoring instances in the layout during LVS (and/or DRC)

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

4 replies • 6429 views
Discussion

AMS simulation fails to generate netlist

Category: Custom IC Design

By Yongqi Hu

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updated over 3 years ago by Yongqi Hu

9 replies • 13763 views
Discussion

set minimum time step for saved data

Category: Custom IC Design

By Darrell L

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updated over 3 years ago by Andrew Beckett

6 replies • 11296 views
Discussion

Different nomenclature for node currents - origin, meaning and how to stick to one only

Category: Custom IC Design

By AncisMichele

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updated over 3 years ago by Andrew Beckett

5 replies • 5561 views
Discussion

How to influence Assembler Monte-Carlo execution regarding Tests in the presence of calcVal?

Category: Custom IC Design

By StephanWeber

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started over 3 years ago

0 replies • 8349 views
Discussion

How to customize ViVA picture export?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by StephanWeber

2 replies • 8900 views
Discussion

visibility toggle feature for instances in layout

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

4 replies • 10264 views
Discussion

Assura isn't created 'run lvs' setting window

Category: Custom IC Design

By ehdwns48

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updated over 3 years ago by ehdwns48

3 replies • 1659 views
Discussion

Recent Files

Category: Custom IC Design

By RicardoGV1

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updated over 3 years ago by Andrew Beckett

3 replies • 8819 views
Discussion

Assembler: Measurement across sweep vs leaf values

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by MohNaj

2 replies • 9942 views
Discussion

Is it possible to hide instances?

Category: Custom IC Design

By Purbayan

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updated over 3 years ago by Andrew Beckett

3 replies • 9543 views
Discussion

Filter in ADE output results table for "eval error" and further filtering

Category: Custom IC Design

By StephanWeber

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started over 3 years ago

0 replies • 1023 views
Discussion

VerilogA $abstime limitation to 2pi

Category: Custom IC Design

By Ajmal Hussian

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updated over 3 years ago by Andrew Beckett

6 replies • 11149 views

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