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Custom IC Design

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  • Discussion

    how to get values of sampling points

    Category: Custom IC Design

    By Holz

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    updated over 4 years ago by Holz

    6 replies • 17219 views
  • Discussion

    My ADE L gives error of not being able to descend into any of the views

    Category: Custom IC Design

    By Svilen64

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    updated over 4 years ago by FormerMember

    3 replies • 12079 views
  • Discussion

    Import several pwl signals through one file?

    Category: Custom IC Design

    By Holz

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    updated over 4 years ago by Holz

    4 replies • 14644 views
  • Discussion

    Cadence Calculator Function for the difference between the abscissa of the intersection of two curves

    Category: Custom IC Design

    By zzzzzzzzzw

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    updated over 4 years ago by FormerMember

    2 replies • 11327 views
  • Discussion

    systemVerilog equivalent of ahdlLib?

    Category: Custom IC Design

    By aicdesigner

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    updated over 4 years ago by aicdesigner

    2 replies • 11337 views
  • Discussion

    How to measure input capacitance?

    Category: Custom IC Design

    By Holz

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    updated over 4 years ago by FormerMember

    3 replies • 17293 views
  • Discussion

    PSS and TRAN jitter results not matching for very simplistic testcase

    Category: Custom IC Design

    By HoWei

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    updated over 4 years ago by Frank Wiedmann

    19 replies • 18844 views
  • Discussion

    TIMEOUT feature

    Category: Custom IC Design

    By naga369

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    started over 4 years ago

    0 replies • 10559 views
  • Discussion

    PLL + PSS + PNOISE convergence

    Category: Custom IC Design

    By HoWei

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    •

    updated over 4 years ago by FormerMember

    17 replies • 27040 views
  • Discussion

    How to treat parasitic device as open for LVS

    Category: Custom IC Design

    By brianbranch

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    updated over 4 years ago by Andrew Beckett

    1 replies • 11404 views
  • Discussion

    WARNING (OCN-6038) Results dc are not available loading OCEAN script

    Category: Custom IC Design

    By Victor Camacho

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    updated over 4 years ago by Andrew Beckett

    3 replies • 12695 views
  • Discussion

    Report CPU time directly in ADE Assembler

    Category: Custom IC Design

    By jehh

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    •

    updated over 4 years ago by Frank Wiedmann

    3 replies • 10739 views
  • Discussion

    Plotting phase spectrum

    Category: Custom IC Design

    By sidt

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    •

    updated over 4 years ago by sidt

    2 replies • 14921 views
  • Discussion

    Post Layout simulation accuracy

    Category: Custom IC Design

    By Fatima65

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    •

    updated over 4 years ago by Frank Wiedmann

    7 replies • 14931 views
  • Discussion

    Virtuoso Cadence crashes when opening layout viewer

    Category: Custom IC Design

    By Eric2020

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    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 11359 views
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