Custom IC Design

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HOW TO CALCULATE CLOCK FREQUENCY OF VPWL VOLTAGE SOURCE

Category: Custom IC Design

By rijalomkar

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updated over 3 years ago by Andrew Beckett

1 replies • 8586 views
Discussion

Ignoring instances in the layout during LVS (and/or DRC)

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

4 replies • 6453 views
Discussion

AMS simulation fails to generate netlist

Category: Custom IC Design

By Yongqi Hu

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updated over 3 years ago by Yongqi Hu

9 replies • 13786 views
Discussion

set minimum time step for saved data

Category: Custom IC Design

By Darrell L

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updated over 3 years ago by Andrew Beckett

6 replies • 11316 views
Discussion

Different nomenclature for node currents - origin, meaning and how to stick to one only

Category: Custom IC Design

By AncisMichele

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updated over 3 years ago by Andrew Beckett

5 replies • 5574 views
Discussion

How to influence Assembler Monte-Carlo execution regarding Tests in the presence of calcVal?

Category: Custom IC Design

By StephanWeber

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started over 3 years ago

0 replies • 8364 views
Discussion

How to customize ViVA picture export?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by StephanWeber

2 replies • 8917 views
Discussion

visibility toggle feature for instances in layout

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

4 replies • 10287 views
Discussion

Assura isn't created 'run lvs' setting window

Category: Custom IC Design

By ehdwns48

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updated over 3 years ago by ehdwns48

3 replies • 1664 views
Discussion

Recent Files

Category: Custom IC Design

By RicardoGV1

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updated over 3 years ago by Andrew Beckett

3 replies • 8838 views
Discussion

Assembler: Measurement across sweep vs leaf values

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by MohNaj

2 replies • 9967 views
Discussion

Is it possible to hide instances?

Category: Custom IC Design

By Purbayan

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updated over 3 years ago by Andrew Beckett

3 replies • 9563 views
Discussion

Filter in ADE output results table for "eval error" and further filtering

Category: Custom IC Design

By StephanWeber

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started over 3 years ago

0 replies • 1024 views
Discussion

VerilogA $abstime limitation to 2pi

Category: Custom IC Design

By Ajmal Hussian

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updated over 3 years ago by Andrew Beckett

6 replies • 11171 views
Discussion

While implementing SENT Rx Tx interface, the operating voltage is 5V in most of the paper for 0.18u technology, I am using 0.03u technology, kindly suggest the suitable voltage for this? cause if I am using high voltage MOS still not working?

Category: Custom IC Design

By CadenSr

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updated over 3 years ago by FormerMember

1 replies • 865 views

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