Custom IC Design

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Discussion

Input referred sampled pnoise

Category: Custom IC Design

By Matthew Love

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updated over 2 years ago by ShawnLogan

3 replies • 6582 views
Discussion

Error using cds_innersrr

Category: Custom IC Design

By elic253

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updated over 2 years ago by elic253

4 replies • 6397 views
Discussion

[Solved]Cannot open layout view due to stuck at "tsmcCdfFormInitCB"

Category: Custom IC Design

By yuh wang

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started over 2 years ago

0 replies • 1642 views
Discussion

Change default plot setting (log-scale & line plot)

Category: Custom IC Design

By ashwinrs

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updated over 2 years ago by Andrew Beckett

1 replies • 2200 views
Discussion

simulations which ran after maestro's check out are getting removed from history when canceling the check out

Category: Custom IC Design

By analog2

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updated over 2 years ago by analog2

2 replies • 1716 views
Discussion

How can I get Verilog-A code of RPI poly-Si TFT model?

Category: Custom IC Design

By Dannny97

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updated over 2 years ago by Andrew Beckett

1 replies • 5769 views
Discussion

Monte Carlo in parametric analysis.

Category: Custom IC Design

By Euller Lucas

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updated over 2 years ago by Euller Lucas

2 replies • 5752 views
Discussion

Glitch

Category: Custom IC Design

By VIRAJ PANCHAL

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updated over 2 years ago by VIRAJ PANCHAL

3 replies • 7311 views
Discussion

ADE Assembler: automatic ADC gain error extraction

Category: Custom IC Design

By NewScreenName

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updated over 2 years ago by Andrew Beckett

11 replies • 11006 views
Discussion

LVS mismatch when transistor body is not detached/integrated

Category: Custom IC Design

By supriyo1985

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updated over 2 years ago by supriyo1985

1 replies • 1843 views
Discussion

How to sample a signal at specific (non-uniform) points in time?

Category: Custom IC Design

By DomiHammerfall

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updated over 2 years ago by DomiHammerfall

7 replies • 9365 views
Discussion

How to plot INL & DNL of converter...?

Category: Custom IC Design

By VIRAJ PANCHAL

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updated over 2 years ago by VIRAJ PANCHAL

2 replies • 3679 views
Discussion

Difference in ADE variable expression evaluation with and without a parametric sweep

Category: Custom IC Design

By ItsMichael

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updated over 2 years ago by Andrew Beckett

4 replies • 7244 views
Discussion

Starting simulations when previous one finished

Category: Custom IC Design

By NewScreenName

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updated over 2 years ago by Andrew Beckett

1 replies • 5829 views
Discussion

ADE L and Spectre environment settings revert to default eah time a simulation is started

Category: Custom IC Design

By PrzemDictador

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updated over 2 years ago by Andrew Beckett

4 replies • 8374 views

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