Custom IC Design

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Discussion

ADE-L asking for license when using "schematic menus"

Category: Custom IC Design

By tkhan

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updated over 15 years ago by tkhan

7 replies • 2915 views
Discussion

ultrasim partitioning error, can I decalre bias node as voltage regulator output?

Category: Custom IC Design

By huber

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updated over 15 years ago by Andre Baguenie

2 replies • 14478 views
Discussion

autosave option in 6.1.3 version

Category: Custom IC Design

By shushan

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updated over 15 years ago by chlascrew

7 replies • 17049 views
Discussion

spectre RF pss sweep error

Category: Custom IC Design

By kivvzhou

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updated over 16 years ago by Andrew Beckett

4 replies • 15881 views
Discussion

ASSURA LVS errors

Category: Custom IC Design

By Dennis Faber

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updated over 16 years ago by Quek

3 replies • 15653 views
Discussion

Operating region

Category: Custom IC Design

By jugemu1234

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updated over 16 years ago by Dennis Faber

4 replies • 77071 views
Discussion

extract specified layout net 5141 (Assura & pvs)

Category: Custom IC Design

By stuso

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updated over 16 years ago by Andrew Beckett

3 replies • 1945 views
Discussion

Ultrasim partitioning guidelines

Category: Custom IC Design

By paulaos

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started over 16 years ago

0 replies • 13617 views
Discussion

Plotting pole/zero results

Category: Custom IC Design

By Grover

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updated over 16 years ago by Andrew Beckett

7 replies • 9525 views
Discussion

Set Context / Calibre RVE?

Category: Custom IC Design

By PolygonSlinger

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updated over 16 years ago by kbhow

2 replies • 17369 views
Discussion

comparission of two GDS

Category: Custom IC Design

By sailesh

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updated over 16 years ago by stuso

5 replies • 19875 views
Discussion

Like to extract Some layout nets new layout (new Cell)

Category: Custom IC Design

By Satya

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updated over 16 years ago by Quek

6 replies • 16072 views
Discussion

Layer grouping in Techfile and acess it through Skill

Category: Custom IC Design

By Satya

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updated over 16 years ago by Andrew Beckett

3 replies • 14960 views
Discussion

vdd not sensed in post-layout simulation

Category: Custom IC Design

By Malolo

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updated over 16 years ago by Andrew Beckett

1 replies • 14578 views
Discussion

Can the open BSIM4 standard provide a means for fair simulator benchmarking?

Category: Custom IC Design

By karbiu

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started over 16 years ago

0 replies • 13537 views

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